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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by: DSP56307DS/D Rev. 0, 8/10/98
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24-BIT DIGITAL SIGNAL PROCESSOR
DSP56307
The Motorola DSP56307, a member of the DSP56300 family of programmable digital signal processors (DSPs), supports wireless infrastructure applications with general filtering operations. The on-chip enhanced filter coprocessor (EFCOP) processes filter algorithms in parallel with core operation, thus increasing overall DSP performance and efficiency. Like the other family members, the DSP56307 uses a high-performance, single-clock-cycle-per-instruction engine (code-compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access controller, as in Figure 1. The DSP56307 offers performance at 100 million instructions (MIPS) per second using an internal 100 MHz clock with a 2.5 volt core and independent 3.3 volt input/output power.
3 16 6 6
Memory Expansion Area
Enhanced Filtering Coprocessor EFCOP
Program RAM 16 K x 24 or (Program RAM 15 K x 24 and Instruction Cache 1024 x 24) PM_EB
SCI Interface
Triple Timer
Host Interface HI08
ESSI Interface
X Data RAM 24 K x 24
Y Data RAM 24 K x 24
PIO_EB
XM_EB
Address Generation Unit Six Channel DMA Unit
YAB XAB PAB DAB
YM_EB
Peripheral Expansion Area
External Address Bus Switch External Bus
18 Address
Bootstrap ROM
24-Bit DSP56300 Core
DDB YDB XDB PDB GDB
Interface
and
13 Control
I - Cache
Control External Data Bus Switch
Internal Data Bus Switch
24 Data
Power Mngmnt. Clock Generator PLL Program Interrupt Controller 2 Program Decode Controller MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Program Address Generator Data ALU 24 x 24+5656-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter 5 JTAG OnCETM
EXTAL XTAL
DE
RESET
PINIT/NMI
AA1367
Figure 1 DSP56307 Block Diagram
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notification.
Not Recommended for New Design
(c)1998 MOTOROLA, INC.
TABLE OF CONTENTS SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 APPENDIX A SIGNALS/CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . A-1 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Index-1 FOR TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com
Data Sheet Conventions
OVERBAR OassertedO OdeassertedO Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage* VIL/VOL VIH/VOH VIH/VOH VIL/VOL
*Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
Not Recommended for New Design
ii DSP56307 Technical Data MOTOROLA
DSP56307 Features
FEATURES High-Performance DSP56300 Core
100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and 3.3 V I/O Object code compatible with the DSP56000 core Highly parallel instruction set Data arithmetic logic unit (ALU) Fully pipelined 24 x 24-bit parallel multiplier-accumulator 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) Conditional ALU instructions 24-bit or 16-bit arithmetic support under software control
Program control unit (PCU) Position independent code (PIC) support Addressing modes optimized for DSP applications (including immediate offsets) On-chip instruction cache controller On-chip memory-expandable hardware stack Nested hardware DO loops Fast auto-return interrupts
Direct memory access (DMA) Six DMA channels supporting internal and external accesses One-, two-, and three- dimensional transfers (including circular buffering) End-of-block-transfer interrupts Triggering from interrupt lines and all peripherals
Phase-locked loop (PLL) Allows change of low power divide factor (DF) without loss of lock Output clock with skew elimination On-Chip Emulation (OnCETM) module Joint test action group (JTAG) test access port (TAP) Address trace mode reflects internal Program RAM accesses at the external port
Hardware debugging support
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data iii
DSP56307 Features
Enhanced Filtering Coprocessor (EFCOP)
The on-chip filtering and echo-cancellation coprocessor runs in parallel to the DSP core.
On-Chip Memories
64 K on-chip RAM total Program RAM, Instruction Cache, X data RAM, and Y data RAM size is programmable:
Instruction Cache Size X Data RAM Size* Y Data RAM Size* Instruction Cache Switch Mode MSW1 MSW0 0/1 0/1 0 0 0 0 1 1 1 1 0/1 0/1 0 0 1 1 0 0 1 1
Program RAM Size
16K x 24-bit 0 24K x 24-bit 24K x 24-bit disabled disabled 1 K x 24-bit 1024 x 24-bit 24K x 24-bit 24K x 24-bit enabled disabled 48K x 24-bit 0 8K x 24-bit 8K x 24-bit disabled enabled 47K x 24-bit 1024 x 24-bit 8K x 24-bit 8K x 24-bit enabled enabled 40K x 24-bit 0 12K x 24-bit 12K x 24-bit disabled enabled 39K x 24-bit 1024 x 24-bit 12K x 24-bit 12K x 24-bit enabled enabled 32K x 24-bit 0 16K x 24-bit 16K x 24-bit disabled enabled 31K x 24-bit 1024 x 24-bit 16K x 24-bit 16K x 24-bit enabled enabled 24K x 24-bit 0 20K x 24-bit 20K x 24-bit disabled enabled 23K x 24-bit 1024 x 24-bit 20K x 24-bit 20K x 24-bit enabled enabled *Includes 4K x 24-bit shared memory (i.e., memory shared by the core and the EFCOP)
192 x 24-bit bootstrap ROM
Off-Chip Memory Expansion
Data memory expansion to two 256K x 24-bit word memory spaces (or up to two 4 M x 24-bit word memory spaces by using the address attribute AA0AA3 signals) Program memory expansion to one 256K x 24-bit words memory space (or up to one 4 M x 24-bit word memory space by using the address attribute AA0AA3 signals) External memory expansion port Chip Select Logic for glueless interface to static random access memory (SRAMs) On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
Not Recommended for New Design
iv DSP56307 Technical Data MOTOROLA
DSP56307 Target Applications
On-Chip Peripherals
Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (e.g., ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) Serial communications interface (SCI) with baud rate generator Triple timer module Up to 34 programmable general purpose input/output (GPIO) pins, depending on which peripherals are enabled

Reduced Power Dissipation
Very low power CMOS design Wait and Stop low-power standby modes Fully static logic, operation frequency down to 0 Hz (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent)
TARGET APPLICATIONS
The DSP56307 is intended for applications requiring a large amount of on-chip memory, such as wireless infrastructure applications. The EFCOP may be used to accelerate general filtering applications, such as echo-cancellation applications, correlation, and general purpose convolution-based algorithms.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data v
DSP56307 Product Documentation
PRODUCT DOCUMENTATION
The three documents listed in the following table are required for a complete description of the DSP56307 and are necessary to design properly with the part. Documentation is available from one of the following locations. (See the back cover for detailed information.) A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW)
See Additional Support in the DSP56300 Family Manual for detailed information on the multiple support options available to you. DSP56307 Documentation
Name Description Detailed description of the DSP56300 family processor core and instruction set Detailed functional description of the DSP56307 memory configuration, operation, and register programming DSP56307 features list and physical, electrical, timing, and package specifications Order Number DSP56300FM/AD
DSP56300 Family Manual DSP56307 User's Manual DSP56307 Technical Data
DSP56307UM/D
DSP56307/D
Not Recommended for New Design
vi DSP56307 Technical Data MOTOROLA
SECTION 1 SIGNALS/CONNECTIONS
SIGNAL GROUPINGS
The input and output signals of the DSP56307 are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56307 signals by functional group. The remainder of this chapter describes the signal pins in each functional group. Table 1-1 DSP56307 Functional Signal Groupings
Functional Group Power (VCC) Ground (GND) Clock PLL Address bus Data bus Bus control Interrupt and mode control Host interface (HI08) Enhanced synchronous serial interface (ESSI) Serial communication interface (SCI) Timer OnCE/JTAG Port
Note: 1. 2. 3. 4.
Number of Signals 20 19 2 3 Port A1 18 24 13 5 Port Port B2 D3 E4 16 12 3 3 6 Ports C and
Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the HI08 port signals multiplexed with the GPIO signals. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. Port E signals are the SCI port signals multiplexed with the GPIO signals.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-1
Signals/Connections Signal Groupings
DSP56307
VCCP VCCQL VCCQH VCCA VCCD VCCC VCCH VCCS GNDP GNDP1 GNDQ GNDA GNDD GNDC GNDH GNDS EXTAL XTAL CLKOUT PCAP After Reset NMI Power Inputs: PLL Core Logic I/O Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer Grounds: PLL PLL Internal Logic Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer Interrupt/M ode Control
4 3 3 4 2 2
During Reset MODA MODB MODC MODD RESET Non-Multiplexe d Bus H0-H7 HA0 HA1 HA2 HCS/HCS Single DS HRW HDS/HDS Single HR HREQ/HREQ HACK/HACK
After Reset IRQA IRQB IRQC IRQD RESET Multiplexed Bus HAD0-HAD7 HAS/HAS HA8 HA9 HA10 Double DS HRD/HRD HWR/HWR Double HR HTRQ/HTRQ HRRQ/HRRQ Port C GPIO PC0-PC2 PC3 PC4 PC5 Port D GPIO PD0-PD2 PD3 PD4 PD5 Port E GPIO PE0 PE1 PE2 Timer GPIO TIO0 TIO1 TIO2 Port B GPIO PB0-PB7 PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15
8
Host Interface (HI08) Port1
4 4 4 2 2
Clock
Enhanced Synchronous Serial Interface Port 0 (ESSI0)2
3
SC00-SC02 SCK0 SRD0 STD0
PLL Enhanced Synchronous Serial Interface Port 1 (ESSI1)2
3
During Reset PINIT
SC10-SC12 SCK1 SRD1 STD1
Port A
A0-A17 D0-D23 AA0-AA3/ RAS0-RAS3 RD WR TA BR BG BB CAS BCLK BCLK Note: 1.
18 24
External Address Bus External Data Bus External Bus Control
Serial Communications Interface (SCI) Port2
RXD TXD SCLK
4
Timers3
TIO0 TIO1 TIO2
2. 3.
TCK TDI TDO OnCE/JTA TMS G Port TRST DE The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or double Host Request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB0-PB15). Signals with dual designations (e.g., HAS/HAS) have configurable polarity. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0-PC5), Port D GPIO signals (PD0-PD5), and Port E GPIO signals (PE0-PE2), respectively. TIO0-TIO2 can be configured as GPIO signals. AA0601
Figure 1-1 Signals Identified by Functional Group
Not Recommended for New Design
1-2 DSP56307 Technical Data MOTOROLA
Signals/Connections Power
POWER
Table 1-2 Power Inputs Power Name VCCP Description PLL PowerNVCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. Quiet Core (Low) PowerNVCCQL is an isolated power for the core processing logic. This input must be isolated externally from all other chip power inputs. The user must provide adequate external decoupling capacitors. Quiet External (High) PowerNVCCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs, except VCCQL. The user must provide adequate decoupling capacitors. Address Bus PowerNVCCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. The user must provide adequate external decoupling capacitors. Data Bus PowerNVCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. The user must provide adequate external decoupling capacitors. Bus Control PowerNVCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. The user must provide adequate external decoupling capacitors. Host PowerNVCCH is an isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. The user must provide adequate external decoupling capacitors. ESSI, SCI, and Timer PowerNVCCS is an isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQL. The user must provide adequate external decoupling capacitors.
VCCQL
VCCQH
VCCA
VCCD
VCCC
VCCH
VCCS
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-3
Signals/Connections Ground
GROUND
Table 1-3 Grounds Ground Name GNDP Description PLL GroundNGNDP is ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip package. PLL Ground 1NGNDP1 is ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. Quiet GroundNGNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Address Bus GroundNGNDA is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. Data Bus GroundNGNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Bus Control GroundNGNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Host GroundNGNDH is an isolated ground for the HI08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. ESSI, SCI, and Timer GroundNGNDS is an isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
GNDP1 GNDQ
GNDA
GNDD
GNDC
GNDH
GNDS
Not Recommended for New Design
1-4 DSP56307 Technical Data MOTOROLA
Signals/Connections Clock
CLOCK
Table 1-4 Clock Signals Signal Name EXTAL Type Input State During Reset Input Signal Description External Clock/Crystal InputNEXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock. Crystal OutputNXTAL connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected.
XTAL
Output
Chip-driven
PLL
Table 1-5 Phase-Locked Loop Signals Signal Name PCAP Type Input State During Reset Input Signal Description PLL CapacitorNPCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. CLKOUT Output Chip-driven Clock OutputNCLKOUT provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-5
Signals/Connections External Memory Expansion Port (Port A)
Table 1-5 Phase-Locked Loop Signals (Continued) Signal Name PINIT Type Input State During Reset Input Signal Description PLL InitialNDuring assertion of RESET, the value of PINIT is written into the PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether the PLL is enabled or disabled. Nonmaskable InterruptNAfter RESET deassertion and during normal instruction processing, this Schmitt-trigger input is the negative-edge-triggered NMI request internally synchronized to CLKOUT.
NMI
Input
EXTERNAL MEMORY EXPANSION PORT (PORT A)
Note: When the DSP56307 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: A0A17, D0D23, AA0/RAS0AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.
External Address Bus
Table 1-6 External Address Bus Signals Signal Name A0A17 Type Output State During Reset Tri-stated Signal Description Address BusNWhen the DSP is the bus master, A0A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0A17 do not change state when external memory spaces are not being accessed.
Not Recommended for New Design
1-6 DSP56307 Technical Data MOTOROLA
Signals/Connections External Memory Expansion Port (Port A)
External Data Bus
Table 1-7 External Data Bus Signals Signal Name D0D23 Type Input/ Output State During Reset Tri-stated Signal Description Data BusNWhen the DSP is the bus master, D0D23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0D23 are tri-stated. These lines have weak keepers to maintain the last state even if all drivers are tri-stated.
External Bus Control
Table 1-8 External Bus Control Signals Signal Name AA0AA3 Type State During Reset Signal Description Address AttributeNWhen defined as AA, these signals can be used as chip selects or additional address lines. The default use defines a priority scheme under which only one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit (Bit 14) of the OMR, the priority mechanism is disabled and the lines can be used together as four external lines that can be decoded externally into 16 chip select signals. Row Address StrobeNWhen defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity. Read EnableNWhen the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0D23). Otherwise, RD is tri-stated. Write EnableNWhen the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0D23). Otherwise, the signals are tri-stated.
Output Tri-stated
RAS0RAS3 Output
RD
Output Tri-stated
WR
Output Tri-stated
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-7
Signals/Connections External Memory Expansion Port (Port A)
Table 1-8 External Bus Control Signals (Continued) Signal Name TA Type Input State During Reset Signal Description
Ignored Input Transfer AcknowledgeNIf the DSP56307 is the bus master and there is no external bus activity, or the DSP56307 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the bus control register (BCR) by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the BCR, whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion; otherwise, improper operation may result. TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the OMR. TA functionality may not be used while performing DRAM type accesses; otherwise, improper operation may result.
Not Recommended for New Design
1-8 DSP56307 Technical Data MOTOROLA
Signals/Connections External Memory Expansion Port (Port A)
Table 1-8 External Bus Control Signals (Continued) Signal Name BR Type State During Reset Signal Description Bus RequestNBR is an active-low output, never tri-stated. BR is asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independently of whether the DSP56307 is a bus master or a bus slave. Bus OparkingO allows BR to be deasserted even though the DSP56307 is the bus master. (See the description of bus OparkingO in the BB signal description.) The bus request hole (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state.
Output Output (deasserted)
BG
Input
Ignored Input Bus GrantNBG is an active-low input. BG must be asserted/deasserted synchronous to CLKOUT for proper operation. BG is asserted by an external bus arbitration circuit when the DSP56307 becomes the next bus master. When BG is asserted, the DSP56307 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. The default operation of this bit requires a setup and hold time as specified in DSP56307 Technical Data (the data sheet). An alternate mode can be invoked: set the asynchronous bus arbitration enable (ABE) bit (Bit 13) in the OMR. When this bit is set, BG and BB are synchronized internally. This eliminates the respective setup and hold time requirements but adds a required delay between the deassertion of an initial BG input and the assertion of a subsequent BG input.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-9
Signals/Connections External Memory Expansion Port (Port A)
Table 1-8 External Bus Control Signals (Continued) Signal Name BB Type State During Reset Signal Description Bus BusyNBB is a bidirectional active-low input/output and must be asserted and deasserted synchronous to CLKOUT. BB indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. Called Obus parking,O this allows the current bus master to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB is done by an Oactive pull-upO method (i.e., BB is driven high and then released and held high by an external pull-up resistor). The default operation of this bit requires a setup and hold time as specified in the DSP56307 Technical Data sheet. An alternate mode can be invoked: set the ABE bit (Bit 13) in the OMR. When this bit is set, BG and BB are synchronized internally. See BG for additional information. BB requires an external pull-up resistor. CAS Output Tri-stated Column Address StrobeNWhen the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the bus mastership enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated. Bus ClockNWhen the DSP is the bus master, BCLK is an active-high output. BCLK is active as a sampling signal when the program address tracing mode is enabled (i.e., the ATE bit in the OMR is set). When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. The BCLK rising edge may be used to sample the internal program memory access on the A0A23 address lines. Bus Clock NotNWhen the DSP is the bus master, BCLK is an active-low output and is the inverse of the BCLK signal. Otherwise, the signal is tri-stated.
Input/ Input Output
BCLK
Output Tri-stated
BCLK
Output Tri-stated
Not Recommended for New Design
1-10 DSP56307 Technical Data MOTOROLA
Signals/Connections Interrupt and Mode Control
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chipOs operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
Table 1-9 Interrupt and Mode Control Signal Name RESET Type Input State During Reset Input Signal Description ResetNRESET is an active-low, Schmitt-trigger input. Deassertion of RESET is internally synchronized to CLKOUT. When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in Olock-step.O When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after power up. Mode Select ANMODA is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request ANAfter reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQA is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQA to exit the wait state. If the processor is in the stop standby state and IRQA is asserted, the processor will exit the stop state.
MODA
Input
Input
IRQA
Input
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-11
Signals/Connections Interrupt and Mode Control
Table 1-9 Interrupt and Mode Control (Continued) Signal Name MODB Type Input State During Reset Input Signal Description Mode Select BNMODB is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request BNAfter reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQB is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQB to exit the wait state. If the processor is in the stop standby state and IRQB is asserted, the processor will exit the stop state. Input Mode Select CNMODC is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request CNAfter reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQC is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQC to exit the wait state. If the processor is in the stop standby state and IRQC is asserted, the processor will exit the stop state.
IRQB
Input
MODC
Input
IRQC
Input
Not Recommended for New Design
1-12 DSP56307 Technical Data MOTOROLA
Signals/Connections HI08
Table 1-9 Interrupt and Mode Control (Continued) Signal Name MODD Type Input State During Reset Input Signal Description Mode Select DNMODD is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request DNAfter reset, this input becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If IRQD is asserted synchronous to CLKOUT, multiple processors can be resynchronized using the WAIT instruction and asserting IRQD to exit the wait state. If the processor is in the stop standby state and IRQD is asserted, the processor will exit the stop state.
IRQD
Input
HI08
The HI08 provides a fast parallel-data-to-8-bit port that may be connected directly to the host bus. The HI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-13
Signals/Connections HI08
Table 1-10 Host Interface Signal Name H0H7 Type Input/ Output State During Reset Tri-stated Signal Description Host DataNWhen the HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, these signals are lines 07 of the data bidirectional, tri-state bus. Host AddressNWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 07 of the address/data bidirectional, multiplexed, tri-state bus. Port B 07NWhen the HI08 is configured as GPIO through the host port control register (HPCR), these signals are individually programmed as inputs or outputs through the HI08 data direction register (HDDR).
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
HAD0HAD7
Input/ Output
PB0PB7
Input or Output
HA0
Input
Input
Host Address Input 0NWhen the HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address StrobeNWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable but is configured active-low (HAS) following reset. Port B 8NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
HAS/HAS
Input
PB8
Input or Output
Not Recommended for New Design
1-14 DSP56307 Technical Data MOTOROLA
Signals/Connections HI08
Table 1-10 Host Interface (Continued) Signal Name HA1 Type Input State During Reset Input Signal Description Host Address Input 1NWhen the HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address 8NWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus. Port B 9NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
HA8
Input
PB9
Input or Output
HA2
Input
Input
Host Address Input 2NWhen the HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. Host Address 9NWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus. Port B 10NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
HA9
Input
PB10
Input or Output
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-15
Signals/Connections HI08
Table 1-10 Host Interface (Continued) Signal Name HRW Type Input State During Reset Input Signal Description Host Read/WriteNWhen HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input. Host Read DataNWhen HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the HRD strobe Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD) after reset. Port B 11NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
HRD/HRD
Input
PB11
Input or Output
HDS/HDS
Input
Input
Host Data StrobeNWhen HI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HDS) following reset. Host Write DataNWhen HI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR) following reset. Port B 12NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
HWR/HWR
Input
PB12
Input or Output
Not Recommended for New Design
1-16 DSP56307 Technical Data MOTOROLA
Signals/Connections HI08
Table 1-10 Host Interface (Continued) Signal Name HCS Type Input State During Reset Input Signal Description Host Chip SelectNWhen HI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. Host Address 10NWhen HI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus. Port B 13NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
HA10
Input
PB13
Input or Output
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-17
Signals/Connections HI08
Table 1-10 Host Interface (Continued) Signal Name HREQ/HREQ Type Output State During Reset Input Signal Description Host RequestNWhen HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host request (HREQ) output. The polarity of the host request is programmable, but is configured as active-low (HREQ) following reset. The host request may be programmed as a driven or open-drain output. Transmit Host RequestNWhen HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ) following reset. The host request may be programmed as a driven or open-drain output. Port B 14NWhen the HI08 is programmed to interface a multiplexed host bus and the signal is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
HTRQ/HTRQ
Output
PB14
Input or Output
Not Recommended for New Design
1-18 DSP56307 Technical Data MOTOROLA
Signals/Connections Enhanced Synchronous Serial Interface 0
Table 1-10 Host Interface (Continued) Signal Name HACK/ HACK Type Input State During Reset Input Signal Description Host AcknowledgeNWhen HI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK) after reset. Receive Host RequestNWhen HI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ) after reset. The host request may be programmed as a driven or open-drain output. Port B 15NWhen the HI08 is configured as GPIO through the HPCR, this signal is individually programmed as an input or output through the HDDR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
HRRQ/ HRRQ
Output
PB15
Input or Output
ENHANCED SYNCHRONOUS SERIAL INTERFACE 0
There are two synchronous serial interfaces (ESSI0 and ESSI1) that provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola serial peripheral interface (SPI).
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-19
Signals/Connections Enhanced Synchronous Serial Interface 0
Table 1-11 Enhanced Synchronous Serial Interface 0 Signal Name SC00 Type Input or Output State During Reset Input Signal Description Serial Control 0NThe function of SC00 is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal will be used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port C 0NThe default configuration following reset is GPIO input PC0. When configured as PC0, signal direction is controlled through the port directions register (PRR0). The signal can be configured as ESSI signal SC00 through the port control register (PCR0).
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PC0
SC01
Input/ Output
Input
Serial Control 1NThe function of this signal is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for transmitter 2 output or for serial I/O flag 1. Port C 1NThe default configuration following reset is GPIO input PC1. When configured as PC1, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC01 through PCR0.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PC1
Input or Output
Not Recommended for New Design
1-20 DSP56307 Technical Data MOTOROLA
Signals/Connections Enhanced Synchronous Serial Interface 0
Table 1-11 Enhanced Synchronous Serial Interface 0 (Continued) Signal Name SC02 Type Input/ Output State During Reset Input Signal Description Serial Control Signal 2NSC02 is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port C 2NThe default configuration following reset is GPIO input PC2. When configured as PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PC2
Input or Output
SCK0
Input/ Output
Input
Serial ClockNSCK0 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the ESSI. The SCK0 is a clock input or output, used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock.
PC3
Input or Output
Port C 3NThe default configuration following reset is GPIO input PC3. When configured as PC3, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SCK0 through PCR0.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-21
Signals/Connections Enhanced Synchronous Serial Interface 0
Table 1-11 Enhanced Synchronous Serial Interface 0 (Continued) Signal Name SRD0 Type Input/ Output State During Reset Input Signal Description Serial Receive DataNSRD0 receives serial data and transfers the data to the ESSI receive shift register. SRD0 is an input when data is being received. Port C 4NThe default configuration following reset is GPIO input PC4. When configured as PC4, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SRD0 through PCR0.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PC4
Input or Output
STD0
Input/ Output
Input
Serial Transmit DataNSTD0 is used for transmitting data from the serial transmit shift register. STD0 is an output when data is being transmitted. Port C 5NThe default configuration following reset is GPIO input PC5. When configured as PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PC5
Input or Output
Not Recommended for New Design
1-22 DSP56307 Technical Data MOTOROLA
Signals/Connections Enhanced Synchronous Serial Interface 1
ENHANCED SYNCHRONOUS SERIAL INTERFACE 1
Table 1-12 Enhanced Serial Synchronous Interface 1 Signal Name SC10 Type Input or Output State During Reset Input Signal Description Serial Control 0NThe function of SC10 is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal will be used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port D 0NThe default configuration following reset is GPIO input PD0. When configured as PD0, signal direction is controlled through the port directions register (PRR1). The signal can be configured as an ESSI signal SC10 through the port control register (PCR1).
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PD0
Input or Output
SC11
Input/ Output
Input
Serial Control 1NThe function of this signal is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1. Port D 1NThe default configuration following reset is GPIO input PD1. When configured as PD1, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC11 through PCR1.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PD1
Input or Output
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-23
Signals/Connections Enhanced Synchronous Serial Interface 1
Table 1-12 Enhanced Serial Synchronous Interface 1 (Continued) Signal Name SC12 Type Input/ Output State During Reset Input Signal Description Serial Control Signal 2NSC12 is used for frame sync I/O. SC12 is the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port D 2NThe default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC12 through PCR1.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PD2
Input or Output
SCK1
Input/ Output
Input
Serial ClockNSCK1 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the ESSI. The SCK1 is a clock input or output used by both the transmitter and receiver in synchronous modes, or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock.
PD3
Input or Output
Port D 3NThe default configuration following reset is GPIO input PD3. When configured as PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
Not Recommended for New Design
1-24 DSP56307 Technical Data MOTOROLA
Signals/Connections SCI
Table 1-12 Enhanced Serial Synchronous Interface 1 (Continued) Signal Name SRD1 Type Input/ Output State During Reset Input Signal Description Serial Receive DataNSRD1 receives serial data and transfers the data to the ESSI receive shift register. SRD1 is an input when data is being received. Port D 4NThe default configuration following reset is GPIO input PD4. When configured as PD4, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SRD1 through PCR1.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PD4
Input or Output
STD1
Input/ Output
Input
Serial Transmit DataNSTD1 is used for transmitting data from the serial transmit shift register. STD1 is an output when data is being transmitted. Port D 5NThe default configuration following reset is GPIO input PD5. When configured as PD5, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal STD1 through PCR1.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PD5
Input or Output
SCI
The SCI provides a full duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-25
Signals/Connections SCI
Table 1-13 Serial Communication Interface Signal Name RXD Type Input State During Reset Input Signal Description Serial Receive DataNThis input receives byte oriented serial data and transfers it to the SCI receive shift register. Port E 0NThe default configuration following reset is GPIO input PE0. When configured as PE0, signal direction is controlled through the SCI port directions register (PRR). The signal can be configured as an SCI signal RXD through the SCI port control register (PCR).
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PE0
Input or Output
TXD
Output
Input
Serial Transmit DataNThis signal transmits data from SCI transmit data register. Port E 1NThe default configuration following reset is GPIO input PE1. When configured as PE1, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal TXD through the SCI PCR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PE1
Input or Output
SCLK
Input/ Output
Input
Serial ClockNThis is the bidirectional Schmitt-trigger input signal providing the input or output clock used by the transmitter and/or the receiver. Port E 2NThe default configuration following reset is GPIO input PE2. When configured as PE2, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal SCLK through the SCI PCR.
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
PE2 Input or Output
Not Recommended for New Design
1-26 DSP56307 Technical Data MOTOROLA
Signals/Connections Timers
TIMERS
Three identical and independent timers are implemented in the DSP56307. Each timer can use internal or external clocking and can either interrupt the DSP56307 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events.
Table 1-14 Triple Timer Signals Signal Name TIO0 Type Input or Output State During Reset Input Signal Description Timer 0 Schmitt-Trigger Input/OutputN When Timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer I/O through the timer 0 control/status register (TCSR0).
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
TIO1
Input or Output
Input
Timer 1 Schmitt-Trigger Input/OutputN When Timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer I/O through the timer 1 control/status register (TCSR1).
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-27
Signals/Connections JTAG and OnCE Interface
Table 1-14 Triple Timer Signals (Continued) Signal Name TIO2 Type Input or Output State During Reset Input Signal Description Timer 2 Schmitt-Trigger Input/OutputN When timer 2 functions as an external event counter or in measurement mode, TIO2 is used as input. When timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer I/O through the timer 2 control/status register (TCSR2).
Note: This signal has a weak keeper to maintain the last state even if all drivers are tri-stated.
JTAG AND OnCE INTERFACE
The DSP56300 family and in particular the DSP56307 support circuit-board test strategies based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or on-chip peripherals. Functions of the OnCE module are provided through the JTAG TAP signals. For programming models, see Section 12 Joint Test Action Group Port and Section 11 On-Chip Emulation Module .
Not Recommended for New Design
1-28 DSP56307 Technical Data MOTOROLA
Signals/Connections JTAG and OnCE Interface
Table 1-15 OnCE/JTAG Interface Signal Name TCK TDI Type Input Input State During Reset Input Input Signal Description Test ClockNTCK is a test clock input signal used to synchronize the JTAG test logic. Test Data InputNTDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. Test Data OutputNTDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode SelectNTMS is an input signal used to sequence the test controllerOs state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. Test ResetNTRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. TRST must be asserted after power up.
TDO
Output
Tri-stated
TMS
Input
Input
TRST
Input
Input
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 1-29
Signals/Connections JTAG and OnCE Interface
Table 1-15 OnCE/JTAG Interface (Continued) Signal Name DE Type Input/ Output State During Reset Input Signal Description Debug EventNDE is an open-drain, bidirectional, active-low signal that provides, as an input, a means of entering the debug mode of operation from an external command controller, and, as an output, a means of acknowledging that the chip has entered the debug mode. This signal, when asserted as an input, causes the DSP56300 core to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for three clock cycles when the chip enters the debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE has an internal pull-up resistor. This is not a standard part of the JTAG TAP controller. The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered the debug mode. All other interface with the OnCE module must occur through the JTAG port.
Not Recommended for New Design
1-30 DSP56307 Technical Data MOTOROLA
SECTION 2 SPECIFICATIONS
INTRODUCTION
The DSP56307 is fabricated in high-density CMOS with transistor-transistor Logic (TTL) compatible inputs and outputs. The DSP56307 specifications are preliminary from design simulations and may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after full characterization and device qualifications are complete.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst-case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a OmaximumO value for a specification will never occur in the same device that has a OminimumO value for another specification, adding a maximum to a minimum represents a condition that can never exist.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-1
Specifications Thermal Characteristics
Table 2-1 Maximum Ratings
Rating1 Supply Voltage: PLL (VCCP) and Core (VCCQL) All other (I/O) All input signal voltages Current drain per pin excluding VCC and GND Operating temperature range Storage temperature
Notes: 1. 2.
Symbol VCCx
Value1, 2
Unit
-0.3 to +3.3
0.3 to +4.0 GND - 0.3 to VCCQH + 0.3 10
V V V mA
VIN I TJ TSTG
-40 to +100 -55 to +150
uC uC
GND = 0 V, VCCQL/VCCP = 2.5 V 0.2 V, I/O VCC = 3.3 0.3 V, TJ = 40C to +100C, CL = 50 pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device.
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter
Notes: 1.
Symbol RJA or JA RJC or JC JT
PBGA Value 51.9 13.1 2.45
PBGA3 Value 29.0 N 1.68
Unit
uC/W uC/W uC/W
2. 3.
Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI G38-87 in natural convection. (SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. The test board has two, 2-ounce signal layers and two 1-ounce solid ground planes internal to the test board.
Not Recommended for New Design
2-2 DSP56307 Technical Data MOTOROLA
Specifications DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics1
Characteristics Supply voltage: Core (VCCQL)9 and PLL (VCCP)
4.
Symbol VCC
Min 2.3 3.0
Typ 2.5 3.3
Max 2.7 3.6
Unit V
I/O (VCCQH, VCCA, VCCD, VCCC, VCCH, and VCCS)10
Input high voltage D0D23, BG, BB, TA MOD2/IRQ2, RESET, PINIT/NMI and all JTAG/ESSI/SCI/Timer/HI08 pins EXTAL3 Input low voltage D0D23, BG, BB, TA, MOD2/IRQ2, RESET, PINIT All JTAG/ESSI/SCI/Timer/HI08 pins EXTAL3 Input leakage current (@ maximum VCCQH / 0.0 V) High impedance (off-state) input current (@ maximum VCCQH / 0.0 V) Output high voltage TTL (IOH = 0.4 mA)4,5 CMOS (IOH = 10 A)4 Output low voltage TTL (Port A IOL = 1.6 mA, non-Port A IOL = 3.2 mA, open-drain pins IOL = 6.7 mA)4,5 CMOS (IOL = 10 A)4 Internal supply In Normal mode In Wait mode7 In Stop mode8 PLL supply current in Stop mode4 Input capacitance4 current6:
VIH VIHP VIHX
2.0 2.0 0.8 x VCCQH
N N N
VCCQH VCCQH + 0.3 VCCQH
V V V
VIL VILP VILX IIN ITSI VOH
0.3 0.3 0.3 10 10
N N N N N
0.8 0.8 0.2 x VCCQH 10 10
V V V A A
2.4 VCCQH 0.01 N
N N N
N N 0.4
V V V
VOL
N ICCI ICCW ICCS N CIN N N N N N
N 120 5 100 1 N
0.01 N N N N 10
V mA mA A mA pF
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-3
Specifications AC Electrical Characteristics
Table 2-3 DC Electrical Characteristics1 (Continued)
Characteristics
Notes: 1. 2. 3.
Symbol
Min
Typ
Max
Unit
VCCQL/VCCP = 2.5 V 0.2 V; I/O VCC = 3.3 0.3 V; TJ = 40uC to +100 uC, CL = 50 pF Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (dc current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 x VCC and the maximum VILX should be no higher than 0.1 x VCC. 4. Periodically sampled and not 100% tested 5. This characteristic does not apply to XTAL and PCAP. 6. Power Consumption Considerations on page SECTION 4-4 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. (For an example, see Appendix A, Power Consumption Benchmark on page APPENDIX A-1.) The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCCQL = 2.5 V at TJ = 100uC. Maximum internal supply current may vary widely and is application dependent. 7. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL and XTAL signals are disabled during Stop state. 8. In order to obtain these results, all inputs not disconnected in Stop mode must be terminated (i.e., not allowed to float). 9. See DSP56307 Errata ES 74. for appropriate operating voltages for appropriate mask sets. 10. See DSP56307 Errata ES93 for appropriate workarounds to data bus drift problem.
AC ELECTRICAL CHARACTERISTICS
The timing waveforms shown in the ac electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of Table 2-3. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signalOs transition. DSP56307 output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively.
INTERNAL CLOCKS
Table 2-4 Internal Clocks, CLKOUT
Expression1, 2 Characteristics Symbol Min Internal operation frequency and CLKOUT with PLL enabled f N Typ (Ef x MF)/ (PDF x DF) Max N
Not Recommended for New Design
2-4 DSP56307 Technical Data MOTOROLA
Specifications Internal Clocks
Table 2-4 Internal Clocks, CLKOUT
Expression1, 2 Characteristics Symbol Min Internal operation frequency and CLKOUT with PLL disabled Internal clock and CLKOUT high period With PLL disabled With PLL enabled and MF 4 With PLL enabled and MF > 4 Internal clock and CLKOUT low period With PLL disabled With PLL enabled and MF 4 With PLL enabled and MF > 4 Internal clock and CLKOUT cycle time with PLL enabled Internal clock and CLKOUT cycle time with PLL disabled Instruction cycle time
Notes: 1.
Typ Ef/2
Max N
f
N
TH
N 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF
ETC N N
N 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF
TL
N 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF N N N
ETC N N ETC x PDF x DF/MF 2 x ETC TC
N 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF N N N
TC TC ICYC
2.
DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle See PLL and Clock Generation in the DSP56300 Family Manual for a detailed discussion of the phase-locked loop.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-5
Specifications External Clock Operation
EXTERNAL CLOCK OPERATION
The DSP56307 system clock may be derived from the on-chip crystal oscillator, as shown in Figure 1 on the cover page, or it may be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL (see Figure 2-2), leaving XTAL physically not connected to the board or socket.
EXTAL R1 XTAL R2 EXTAL R XTAL
C
XTAL1
C
C
XTAL1
C
Fundamental Frequency Fork Crystal Oscillator Suggested Component Values:
fOSC = 32.768 kHz R1 = 3.9 M 10% C = 22 pF 20% R2 = 200 k 10% Calculations were done for a 32.768 kHz crystal with the following parameters: a load capacitance (CL) of 12.5 pF, a shunt capacitance (C0) of 1.8 pF, a series resistance of 40 k, and a drive level of 1 W.
Fundamental Frequency Crystal Oscillator Suggested Component Values:
fOSC = 4 MHz R = 680 k 10% C = 56 pF 20% fOSC = 20 MHz R = 680 k 10% C = 22 pF 20%
Calculations were done for a 4/20 MHz crystal with the following parameters: a CLof 30/20 pF, a C0 of 7/6 pF, a series resistance of 100/20 , and a drive level of 2 mW.
AA1071
Figure 2-1 Crystal Oscillator Circuits
Not Recommended for New Design
2-6 DSP56307 Technical Data MOTOROLA
Specifications External Clock Operation
VIHC EXTAL VILC ETH 2 4 5 CLKOUT With PLL Disabled 7 CLKOUT With PLL Enabled 6a 6b 7
AA0459
Midpoint
ETL
3 ETC 5
Note:
The midpoint is 0.5 (VIHC + VILC).
Figure 2-2 External Clock Timing Table 2-5 Clock Operation
100 MHz No. 1 Characteristics Frequency of EXTAL (EXTAL pin frequency) The rise and fall time of this external clock should be 3 ns maximum. EXTAL input high1, 2 With PLL disabled (46.7%53.3% duty cycle3) With PLL enabled (42.5%57.5% duty cycle3) EXTAL input low1, 2 With PLL disabled (46.7%53.3% duty cycle3) With PLL enabled (42.5%57.5% duty cycle3) EXTAL cycle time2 With PLL disabled With PLL enabled CLKOUT change from EXTAL fall with PLL disabled Symbol Min Ef 0 Max 100.0
2
ETH
4.67 ns 4.25 ns
157.0 s
3
ETL
4.67 ns 4.25 ns
157.0 s
4
ETC N
10.00 ns 10.00 ns 273.1 s 4.3 ns 11.0 ns
5
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-7
Specifications External Clock Operation
Table 2-5 Clock Operation (Continued)
100 MHz No. 6 Characteristics CLKOUT rising edge from EXTAL rising edge with PLL enabled (MF = 1, PDF = 1, Ef > 15 MHz)4,5 CLKOUT falling edge from EXTAL rising edge with PLL enabled (MF = 2 or 4, PDF = 1, Ef > 15 MHz)4,5 CLKOUT falling edge from EXTAL falling edge with PLL enabled (MF 4, PDF 1, Ef / PDF > 15 MHz)4,5 7 Instruction cycle time = ICYC = TC6 (See Table 2-4.) (46.7%53.3% duty cycle) With PLL disabled With PLL enabled
1. 2. 3.
Symbol Min 0.0 ns Max 1.8 ns
0.0 ns
1.8 ns
0.0 ns
1.8 ns
ICYC 20.0 ns 10.00 ns 8.53 s
Notes:
4. 5. 6.
Measured at 50% of the input transition The maximum value for PLL enabled is given for minimum VCO and maximum MF. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. Periodically sampled and not 100% tested The skew is not guaranteed for any other MF value. The maximum value for PLL enabled is given for minimum VCO and maximum DF.
Not Recommended for New Design
2-8 DSP56307 Technical Data MOTOROLA
Specifications PLL Characteristics
PLL CHARACTERISTICS
Table 2-6 PLL Characteristics
100 MHz Characteristics Recommended VCO frequency when PLL enabled (MF x Ef x 2/PDF) Min 30 Max 200 MHz Unit
PLL external capacitor (PCAP pin to VCCP) (CPCAP) @ MF 4 (MF x 680) - 120 (MF x 580) - 100 (MF x 780) - 140 @ MF > 4 MF x 1100 MF x 830 MF x 1470
Note:
pF pF
CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (500 x MF) 150, for MF 4, or 690 x MF, for MF > 4.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-9
Specifications Reset, Stop, Mode Select, and Interrupt Timing
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing1
100 MHz No. 8 9 Characteristics Delay from RESET assertion to all pins at reset value2 Required RESET duration3 Power on, external clock generator, PLL disabled Power on, external clock generator, PLL enabled Power on, internal oscillator During STOP, XTAL disabled (PCTL Bit 16 = 0) During STOP, XTAL enabled (PCTL Bit 16 = 1) During normal operation Expression Min N N Max 26.0 ns Unit
50 x ETC 1000 x ETC 75000 x ETC 75000 x ETC 2.5 x TC 2.5 x TC
500.0 10.0 0.75 0.75 25.0 25.0
N N N N N N
ns s ms ms ns ns
10 Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)4 Minimum Maximum 11 Synchronous reset set-up time from RESET deassertion to CLKOUT Transition 1 Minimum Maximum 12 Synchronous reset deasserted, delay time from the CLKOUT Transition 1 to the first external address output Minimum Maximum 13 Mode select setup time 14 Mode select hold time 15 Minimum edge-triggered interrupt request assertion width 16 Minimum edge-triggered interrupt request deassertion width
3.25 x TC + 2.0 20.25 TC + 7.50
34.5 N N 211.5
ns ns
TC
5.9 N
N 10.0
ns ns
3.25 x TC + 1.0 20.25 TC + 5.0 N N N N
33.5 N N 207.5 30.0 0.0 6.6 6.6 N N N N
ns ns ns ns ns ns
Not Recommended for New Design
2-10 DSP56307 Technical Data MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing1 (Continued)
100 MHz No. Characteristics Expression Min 17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid Caused by first interrupt instruction fetch Caused by first interrupt instruction execution 18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution 19 Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts5,6,7 20 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts5,6,7 21 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts5,6,7 DRAM for all WS SRAM WS = 1 SRAM WS = 2, 3 SRAM WS 4 22 Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, NMI assertion to the CLKOUT Transition 2 23 Synchronous interrupt delay time from the CLKOUT Transition 2 to the first external address output valid caused by the first instruction fetch after coming out of Wait Processing state Minimum Maximum 24 Duration for IRQA assertion to recover from Stop state Max Unit
4.25 x TC + 2.0 7.25 x TC + 2.0 10 x TC + 5.0
44.5 74.5 105.0
N N N
ns ns ns
(WS + 3.75) x TC 10.94
N
see note 8
ns
(WS + 3.25) x TC 10.94
N
see note 8
ns
(WS + 3.5) x TC 10.94 (WS + 3.5) x TC 10.94 (WS + 3) x TC 10.94 (WS + 2.5) x TC 10.94 N
N N N N 5.9
see note 8
ns ns ns ns ns
TC
9.25 x TC + 1.0 24.75 x TC + 5.0 N
93.5 N N 252.5 5.9 N
ns ns ns
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-11
Specifications Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing1 (Continued)
100 MHz No. Characteristics Expression Min Max Unit
25 Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 8 PLL is not active during Stop PLC x ETC x PDF + (128 K - PLC/2) x TC 1.3 13.6 (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) PLL is not active during Stop PLC x ETC x PDF + (23.75 0.5) x TC 232.5 12.3 (PCTL Bit 17 = 0) and Stop ns ms delay is not enabled (OMR Bit 6 = 1) (8.25 0.5) x TC PLL is active during Stop 77.5 87.5 (PCTL Bit 17 = 1) (Implies No Stop Delay) 26 Duration of level sensitive IRQA assertion to insure interrupt service (when exiting Stop)2, 8 PLL is not active during Stop PLC x ETC x PDF + (128K - PLC/2) x TC 13.6 (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) PLL is not active during Stop PLC x ETC x PDF + (20.5 0.5) x TC 12.3 (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) PLL is active during Stop 5.5 x TC 55.0 (PCTL Bit 17 = 1) (implies no Stop delay) 27 Interrupt Requests Rate HI08, ESSI, SCI, Timer DMA IRQ, NMI (edge trigger) IRQ, NMI (level trigger) 28 DMA Requests Rate Data read from HI08, ESSI, SCI Data write to HI08, ESSI, SCI Timer IRQ, NMI (edge trigger) 29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid 12TC 8TC 8TC 12TC 6TC 7TC 2TC 3TC 4.25 x TC + 2.0 N N N N N N N N 44.0
ms
ns
N
ms
N
ms
N
ns
120.0 80.0 80.0 120.0 60.0 70.0 20.0 30.0 N
ns ns ns ns ns ns ns ns ns
Not Recommended for New Design
2-12 DSP56307 Technical Data MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing1 (Continued)
100 MHz No.
Notes: 1. 2. 3.
Characteristics
Expression Min Max
Unit
VCCQL = 2.5 V 0.25 V; TJ = 40uC to +100uC, CL = 50 pF Periodically sampled and not 100% tested For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the VCC is valid, but the other Orequired RESET durationO conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock When fast interrupts and IRQA are being used, then IRQB, IRQC, and IRQD are defined as level-sensitive; timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, we recommend the deasserted edge-triggered mode when fast interrupts are being used. Long interrupts are recommended when any level-sensitive mode is being used. WS = number of wait states (measured in clock cycles, number of TC) Use expression to compute maximum value. This timing depends on several settings: For PLL disable, if the internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) is being used and the oscillator is disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to insure the oscillator is stable before programs are executed. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case. For PLL disable, if the internal oscillator (PCTL Bit 16 = 0) is being used and the oscillator is enabled during Stop (PCTL Bit 17=1), then no stabilization delay is required, and recovery time will be minimal (i.e., OMR Bit 6 setting is ignored). For PLL disable, if the external clock (PCTL Bit 16 = 1) is being used, no stabilization delay is required, and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovery from Stop requires the PLL to be locked. The duration of the PLL lock procedure (i.e., the PLL Lock Cycles (PLC)) may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency. During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well.
4. 5.
6. 7. 8.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-13
Specifications Reset, Stop, Mode Select, and Interrupt Timing
VIH RESET
9 8 All Pins Reset Value
10
A0-A17
First Fetch
AA0460
Figure 2-3 Reset Timing
CLKOUT
11 RESET 12
A0-A17
AA0461
Figure 2-4 Synchronous Reset Timing
Not Recommended for New Design
2-14 DSP56307 Technical Data MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
A0-A17
First Interrupt Instruction Execution/Fetch
RD 20
WR 21
IRQA, IRQB, IRQC, IRQD, NMI
17
19
a) First Interrupt Instruction Execution
General Purpose I/O
18 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O
AA0462
Figure 2-5 External Fast Interrupt Timing
IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI
16
AA0463
Figure 2-6 External Interrupt Timing (Negative Edge-Triggered)
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-15
Specifications Reset, Stop, Mode Select, and Interrupt Timing
CLKOUT
IRQA, IRQB, IRQC, IRQD, NMI
22
23 A0-A17
AA0464
Figure 2-7 Synchronous Interrupt from Wait State Timing
VIH
RESET 13 14 VIH MODA, MODB, MODC, MODD, PINIT VIL VIH VIL
IRQA, IRQB, IRQC, IRQD, NMI
AA0465
Figure 2-8 Operating Mode Select Timing
24 IRQA
25 A0-A17 First Instruction Fetch
AA0466
Figure 2-9 Recovery from Stop State Using IRQA
Not Recommended for New Design
2-16 DSP56307 Technical Data MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
26 IRQA
25 A0-A17
First IRQA Interrupt Instruction Fetch
AA0467
Figure 2-10 Recovery from Stop State Using IRQA Interrupt Service
A0-A17
DMA Source Address
RD
WR
29
IRQA, IRQB, IRQC, IRQD, NMI
First Interrupt Instruction Execution
AA1104
Figure 2-11 External Memory Access (DMA Source) Timing
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-17
Specifications External Memory Interface (Port A)
EXTERNAL MEMORY INTERFACE (PORT A)
SRAM Timing
Table 2-8 SRAM Read and Write Accesses
No. Characteristics Symbol tRC, tWC Expression1, 2 (WS + 1) x TC - 4.0 [1 WS 3] (WS + 2) x TC - 4.0 [4 WS 7] (WS + 3) x TC - 4.0 [WS 8] 100 MHz: 0.25 x TC - 2.4 [WS = 1] All frequencies: 0.75 x TC - 4.0 [2 WS 3] 1.25 x TC - 4.0 [WS 4] 1.5 x TC - 4.5 [WS = 1] WS x TC - 4.0 [2 WS 3] (WS - 0.5) x TC - 4.0 [WS 4] 100 MHz: 0.25 x TC - 2.4 [1 WS 3] All frequencies: 1.25 x TC - 4.0 [4 WS 7] 2.25 x TC - 4.0 [WS 8] 100 MHz: (WS + 0.75) x TC - 8.0 [WS 1] 100 MHz: (WS + 0.25) x TC - 8.0 [WS 1] 100 MHz Unit Min 16.0 56.0 106.0 Max N N N ns ns ns
100 Address valid and AA assertion pulse width
101 Address and AA valid to WR assertion
tAS
0.1 3.5 8.5 10.5 16.0 31.0 0.1 8.5 18.5 N
N N N N N N N N N 9.5
ns ns ns ns ns ns ns ns ns ns
102 WR assertion pulse width 103 WR deassertion to address not valid
tWP
tWR
104 Address and AA valid to input data valid 105 RD assertion to input data valid 106 RD deassertion to data not valid (data hold time) 107 Address valid to WR deassertion 108 Data valid to WR deassertion (data setup time)
tAA, tAC
tOE
N 0.0
4.5 N
ns ns
tOHZ
tAW
(WS + 0.75) x TC - 4.0 [WS 1]
13.5
N
ns
tDS (tDW) 100 MHz: (WS - 0.25) x TC - 2.75 [WS 1]
4.8
N
ns
Not Recommended for New Design
2-18 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-8 SRAM Read and Write Accesses (Continued)
No. Characteristics Symbol tDH Expression1, 2 100 MHz: 0.25 x TC - 2.4 [1 WS 3] All frequencies: 1.25 x TC - 3.8 [4 WS 7] 2.25 x TC - 3.8 [WS 8] 0.75 x TC - 3.7 [WS = 1] 0.25 x TC - 3.7 [2 WS 3] -0.25 x TC - 3.7 [WS 4] 0.25 x TC + 0.2 [1 WS 3] 1.25 x TC + 0.2 [4 WS 7] 2.25 x TC + 0.2 [WS 8] 1.25 x TC - 4.0 [1 WS 3] 2.25 x TC - 4.0 [4 WS 7] 3.25 x TC - 4.0 [WS 8] 0.75 x TC - 4.0 [1 WS 3] 1.75 x TC - 4.0 [4 WS 7] 2.75 x TC - 4.0 [WS 8] 0.5 x TC - 3.5 [WS = 1] TC - 3.5 [2 WS 3] 2.5 x TC - 3.5 [4 WS 7] 3.5 x TC - 3.5 [WS 8] 0.5 x TC - 4 (WS + 0.25) x TC - 3.8 0.25 x TC - 3.0 [1 WS 3] 1.25 x TC - 3.0 [4 WS 7] 2.25 x TC - 3.0 [WS 8] 100 MHz Unit Min 0.1 8.7 18.7 3.8 1.2 6.2 N N N 8.5 18.5 28.5 3.5 13.5 23.5 1.5 6.5 21.5 31.5 1.0 8.7 0.0 9.5 19.5 Max N N N N N N 2.7 12.7 22.7 N N N N N N N N N N N N N N N ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
109 Data hold time from WR deassertion
110 WR assertion to data active 111 WR deassertion to data high impedance 112 Previous RD deassertion to data active (write) 113 RD deassertion time
N
N
N
N
114 WR deassertion time
N
115 Address valid to RD assertion 116 RD assertion pulse width 117 RD deassertion to address not valid
Notes: 1. 2.
N N N
WS is the number of wait states specified in the BCR. VCCQL = 2.5 V 0.25 V; TJ = 40uC to +100 uC, CL = 50 pF
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-19
Specifications External Memory Interface (Port A)
100 A0-A17 AA0-AA3 113 RD 115 WR 104 D0-D23 Data In 105 106 116 117
AA0468
Figure 2-12 SRAM Read Access
100 A0-A17 AA0-AA3 107 101 WR 114 RD 108 110 112 D0-D23 Data Out
AA0469
102
103
111 109
Figure 2-13 SRAM Write Access
Not Recommended for New Design
2-20 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
DRAM Timing
The selection guides provided in Figure 2-14 and in Figure 2-17 on page SECTION 2-32 should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when page mode DRAM is being used. However, a designer may use the information in the appropriate table to evaluate whether fewer wait states might be used; a designer may determine which timing prevents operation at 100 MHz, run the chip at a slightly lower frequency (e.g., 95 MHz), use faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance.
DRAM Type (tRAC ns)
Note:
This figure should be used for primary selection. For exact and detailed timings, see the following tables.
100
80
70
60
50 40 66 80 100 120
Chip Frequency (MHz)
1 Wait States 2 Wait States
3 Wait States 4 Wait States
AA0472
Figure 2-14 DRAM Page Mode Wait States Selection Guide
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-21
Specifications External Memory Interface (Port A)
Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3
No. 131 132 133 134 135 136 137 138 Characteristics Page mode cycle time CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS deassertion4 BRW[1:0] = 00 BRW[1:0] = 01 BRW[1:0] = 10 BRW[1:0] = 11 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion Symbol tPC tCAC tAA tOFF tRSH tRHCP tCAS tCRP 1.75 x TC - 6.0 3.25 x TC - 6.0 4.25 x TC - 6.0 6.25 x TC 6.0 tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL 0.5 x TC - 4.0 0.5 x TC - 4.0 0.75 x TC - 4.0 2 x TC - 4.0 0.75 x TC - 3.8 0.25 x TC - 3.7 0.5 x TC - 4.2 1.5 x TC - 4.5 1.75 x TC - 4.3 81.5 156.5 206.5 306.5 21.0 21.0 33.5 96.0 33.7 8.8 20.8 70.5 83.2 N N N N N N N N N N N N N 52.3 102.2 135.5 202.1 12.7 12.7 21.0 62.7 21.2 4.6 12.5 45.5 54.0 N N N N N N N N N N N N N ns ns ns ns ns ns ns ns ns ns ns ns ns Expression 1.25 x TC TC - 7.5 1.5 x TC - 7.5 N 0.75 x TC - 4.0 2 x TC - 4.0 0.75 x TC - 4.0 20 MHz6 Min 62.5 N N 0.0 33.5 96.0 33.5 Max N 42.5 67.5 N N N N 30 MHz6 Min 41.7 N N 0.0 21.0 62.7 21.0 Max N 25.8 42.5 N N N N ns ns ns ns ns ns ns Unit
139 140 141 142 143 144 145 146 147
Not Recommended for New Design
2-22 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3
No. 148 149 150 151 152 153 154 155 156
Notes:
Characteristics WR assertion to CAS deassertion Data valid to CAS assertion (Write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid 5 WR assertion to data active WR deassertion to data high impedance
1. 2. 3. 4. 5. 6.
Symbol tCWL tDS tDH tWCS tROH tGA tGZ N N
Expression 1.75 x TC - 4.3 0.25 x TC - 4.0 0.75 x TC - 4.0 TC - 4.3 1.5 x TC - 4.0 TC - 7.5 N 0.75 x TC - 0.3 0.25 x TC
20 MHz6 Min 83.2 8.5 33.5 45.7 71.0 N 0.0 37.2 N Max N N N N N 42.5 N N 12.5
30 MHz6 Min 54.0 4.3 21.0 29.0 46.0 N 0.0 24.7 N Max N N N N N 25.8 N N 8.3
Unit ns ns ns ns ns ns ns ns ns
The number of wait states for page mode access is specified in the DCR. The refresh period is specified in the DCR. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 2 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Reduced DSP clock speed allows use of page mode DRAM with one wait state (see Figure 2-14).
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-23
Specifications External Memory Interface (Port A)
Table 2-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4, 5
66 MHz No. Characteristics Symbol tPC tCAC Expression Min 131 Page mode cycle time 132 CAS assertion to data valid (read) 2.75 x TC 66 MHz: 1.5 x TC - 7.5 80 MHz: 1.5 x TC - 6.5 66 MHz: 2.5 x TC - 7.5 80 MHz: 2.5 x TC - 6.5 N 1.75 x TC - 4.0 3.25 x TC - 4.0 1.5 x TC - 4.0 41.7 N N N N 0.0 22.5 45.2 18.7 Max N 15.2 N 30.4 N N N N N Min 34.4 N N N N 0.0 17.9 36.6 14.8 Max N N 12.3 N 24.8 N N N N ns ns ns ns ns ns ns ns ns 80 MHz Unit
133 Column address valid to data valid (read)
tAA
134 CAS deassertion to data not valid (read hold time) 135 Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width 138 Last CAS deassertion to RAS deassertion6 BRW[1:0] = 00 BRW[1:0] = 01 BRW[1:0] = 10 BRW[1:0] = 11 139 CAS deassertion pulse width 140 Column address valid to CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion 145 CAS assertion to WR deassertion 146 WR assertion pulse width
tOFF tRSH tRHCP tCAS tCRP
2.0 x TC - 6.0 3.5 x TC - 6.0 4.5 x TC - 6.0 6.5 x TC - 6.0 tCP tASC tCAH tRAL tRCS tRCH tWCH tWP 1.25 x TC - 4.0 TC - 4.0 1.75 x TC - 4.0 3 x TC - 4.0 1.25 x TC - 3.8 0.5 x TC - 3.7 1.5 x TC - 4.2 2.5 x TC - 4.5
24.4 47.2 62.4 92.8 14.9 11.2 22.5 41.5 15.1 3.9 18.5 33.4
N N N N N N N N N N N N
19.0 37.8 50.3 75.3 11.6 8.5 17.9 33.5 11.8 2.6 14.6 26.8
N N N N N N N N N N N N
ns ns ns ns ns ns ns ns ns ns ns ns
Not Recommended for New Design
2-24 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4, 5 (Continued)
66 MHz No. Characteristics Symbol tRWL tCWL tDS Expression Min 147 Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (write) 2.75 x TC - 4.3 2.5 x TC - 4.3 66 MHz: 0.25 x TC - 3.7 80 MHz: 0.25 x TC - 3.0 1.75 x TC - 4.0 TC - 4.3 2.5 x TC - 4.0 66 MHz: 1.75 x TC - 7.5 80 MHz: 1.75 x TC - 6.5 N 0.75 x TC - 0.3 0.25 x TC 37.4 33.6 Max N N Min 30.1 27.0 Max N N ns ns 80 MHz Unit
0.1 N 22.5 10.9 33.9
N N N N N
N 0.1 17.9 8.2 27.3
N N N N N
ns ns ns ns ns
150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion 152 Last RD assertion to RAS deassertion 153 RD assertion to data valid
tDH tWCS tROH tGA
N N 0.0 11.1 N
19.0 N N N 3.8
N N 0.0 9.1 N
N 15.4 N N 3.1
ns ns ns ns ns
154 RD deassertion to data not valid7 155 WR assertion to data active 156 WR deassertion to data high impedance
Notes: 1. 2. 3. 4. 5. 6. 7.
tGZ N N
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56307. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). There are not any DRAMs fast enough to fit two wait states in Page mode at 100MHz (see Figure 2-14). BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-25
Specifications External Memory Interface (Port A)
Table 2-11 DRAM Page Mode Timings, Three Wait States1, 2, 3, 4
66 MHz No. Characteristics Symbol tPC tCAC Expression Min Max Min Max Min Max 131 Page mode cycle time 132 CAS assertion to data valid (read) 3.5 x TC 66 MHz: 2 x TC - 7.5 80 MHz: 2 x TC - 6.5 100 MHz: 2 x TC - 5.7 66 MHz: 3 x TC - 7.5 80 MHz: 3 x TC - 6.5 100 MHz: 3 x TC - 5.7 N 2.5 x TC - 4.0 4.5 x TC - 4.0 2 x TC - 4.0 53.0 N N N N N N 0.0 33.9 64.2 26.3 N 22.8 N N 37.9 N N N N N N 43.8 N N N N N N 0.0 27.3 52.3 21.0 N N 18.5 N N 31.0 N N N N N 35.0 N N N N N N 0.0 21.0 41.0 16.0 N N N 14.3 N N 24.3 N N N N ns ns ns ns ns ns ns ns ns ns ns 80 MHz 100 MHz Unit
133 Column address valid to data valid (read)
tAA
134 CAS deassertion to data not valid (read hold time) 135 Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width 138 Last CAS deassertion to RAS deassertion5 BRW[1:0] = 00 BRW[1:0] = 01 BRW[1:0] = 10 BRW[1:0] = 11 139 CAS deassertion pulse width 140 Column address valid to CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion
tOFF tRSH tRHCP tCAS tCRP
2.25 x TC - 6.0 3.75 x TC - 6.0 4.75 x TC - 6.0 6.75 x TC - 6.0 tCP tASC tCAH tRAL tRCS tRCH 1.5 x TC - 4.0 TC - 4.0 2.5 x TC - 4.0 4 x TC - 4.0 1.25 x TC - 3.8 0.75 x TC - 3.7
28.2 51.0 66.2 96.6 18.7 11.2 33.9 56.6 15.1 7.7
N N N N N N N N N N
22.2 40.9 53.4 78.4 14.8 8.5 27.3 46.0 11.8 5.7
N N N N N N N N N N
16.5 31.5 41.5 61.5 11.0 6.0 21.0 36.0 8.7 3.8
N N N N N N N N N N
ns ns ns ns ns ns ns ns ns ns
Not Recommended for New Design
2-26 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-11 DRAM Page Mode Timings, Three Wait States1, 2, 3, 4
66 MHz No. Characteristics Symbol tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA Expression Min Max Min Max Min Max 145 CAS assertion to WR deassertion 146 WR assertion pulse width 147 Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (write) 150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion 152 Last RD assertion to RAS deassertion 153 RD assertion to data valid 2.25 x TC - 4.2 3.5 x TC - 4.5 3.75 x TC - 4.3 3.25 x TC - 4.3 0.5 x TC - 4.0 2.5 x TC - 4.0 1.25 x TC - 4.3 3.5 x TC - 4.0 66 MHz: 2.5 x TC - 7.5 80 MHz: 2.5 x TC - 6.5 100 MHz: 2.5 x TC - 5.7 N 0.75 x TC - 0.3 0.25 x TC 29.9 48.5 52.5 44.9 3.6 33.9 14.6 49.0 N N N N N N N N 23.9 39.3 42.6 36.3 2.3 27.3 11.3 39.8 N N N N N N N N 18.3 30.5 33.2 28.2 1.0 21.0 8.2 31.0 N N N N N N N N ns ns ns ns ns ns ns ns 80 MHz 100 MHz Unit
N N N 0.0 11.1 N
30.4 N N N N 3.8
N N N 0.0 9.1 N
N 24.8 N N N 3.1
N N N 0.0 7.2 N
N N 19.3 N N 2.5
ns ns ns ns ns ns
154 RD deassertion to data not valid6 155 WR assertion to data active 156 WR deassertion to data high impedance
Notes: 1. 2. 3. 4. 5. 6.
tGZ N N
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56307. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-27
Specifications External Memory Interface (Port A)
Table 2-12 DRAM Page Mode Timings, Four Wait States1, 2, 3, 4
66 MHz No. Characteristics Symbol tPC tCAC Expression Min Max Min Max Min Max 131 Page mode cycle time 132 CAS assertion to data valid (read) 4.5 x TC 66 MHz: 2.75 x TC - 7.5 80 MHz: 2.75 x TC - 6.5 100 MHz: 2.75 x TC - 5.7 66 MHz: 3.75 x TC - 7.5 80 MHz: 3.75 x TC - 6.5 100 MHz: 3.75 x TC - 5.7 N 3.5 x TC - 4.0 6 x TC - 4.0 2.5 x TC - 4.0 68.2 N N N N N N 0.0 49.0 86.9 33.9 N 34.2 N N 49.3 N N N N N N 56.3 N N N N N N 0.0 39.8 71.0 27.3 N N 27.9 N N 40.4 N N N N N 45.0 N N N N N N 0.0 31.0 56.0 21.0 N N N 21.8 N N 31.8 N N N N ns ns ns ns ns ns ns ns ns ns ns 80 MHz 100 MHz Unit
133 Column address valid to data valid (read)
tAA
134 CAS deassertion to data not valid (read hold time) 135 Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width 138 Last CAS deassertion to RAS deassertion5 BRW[1:0] = 00 BRW[1:0] = 01 BRW[1:0] = 10 BRW[1:0] = 11 139 CAS deassertion pulse width 140 Column address valid to CAS assertion 141 CAS assertion to column address not valid 142 Last column address valid to RAS deassertion 143 WR deassertion to CAS assertion 144 CAS deassertion to WR assertion
tOFF tRSH tRHCP tCAS tCRP
2.75 x TC - 6.0 4.25 x TC - 6.0 5.25 x TC - 6.0 6.25 x TC - 6.0 tCP tASC tCAH tRAL tRCS tRCH 2 x TC - 4.0 TC - 4.0 3.5 x TC - 4.0 5 x TC - 4.0 1.25 x TC - 3.8 1.25 x TC - 3.7
35.8 58.6 73.8 89.0 26.3 11.2 49.0 71.8 15.1 15.2
N N N N N N N N N N
28.4 47.2 59.7 72.2 21.0 8.5 39.8 58.5 11.8 11.9
N N N N N N N N N N
21.5 36.5 46.5 56.5 16.0 6.0 31.0 46.0 8.7 8.8
N N N N N N N N N N
ns ns ns ns ns ns ns ns ns ns
Not Recommended for New Design
2-28 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-12 DRAM Page Mode Timings, Four Wait States1, 2, 3, 4 (Continued)
66 MHz No. Characteristics Symbol tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA Expression Min Max Min Max Min Max 145 CAS assertion to WR deassertion 146 WR assertion pulse width 147 Last WR assertion to RAS deassertion 148 WR assertion to CAS deassertion 149 Data valid to CAS assertion (write) 150 CAS assertion to data not valid (write) 151 WR assertion to CAS assertion 152 Last RD assertion to RAS deassertion 153 RD assertion to data valid 3.25 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 3.75 x TC - 4.3 0.5 x TC - 4.0 3.5 x TC - 4.0 1.25 x TC - 4.3 4.5 x TC - 4.0 66 MHz: 3.25 x TC - 7.5 80 MHz: 3.25 x TC - 6.5 100 MHz: 3.25 x TC - 5.7 N 0.75 x TC - 0.3 0.25 x TC 45.0 63.7 67.7 52.5 3.6 49.0 14.6 64.2 N N N N N N N N 36.4 51.8 55.1 42.6 2.3 39.8 11.3 52.3 N N N N N N N N 28.3 40.5 43.2 33.2 1.0 31.0 8.2 41.0 N N N N N N N N ns ns ns ns ns ns ns ns 80 MHz 100 MHz Unit
N N N 0.0 11.1 N
41.7 N N N N 3.8
N N N 0.0 9.1 N
N 34.1 N N N 3.1
N N N 0.0 7.2 N
N N 26.8 N N 2.5
ns ns ns ns ns ns
154 RD deassertion to data not valid6 155 WR assertion to data active 156 WR deassertion to data high impedance
Notes: 1. 2. 3. 4. 5. 6.
tGZ N N
The number of wait states for page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56307. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-29
Specifications External Memory Interface (Port A)
RAS 136 131 CAS 137 140 141 A0-A17
Row Add Column Address Column Address
135
139
138 142
Last Column Address
151 145
144
143 147
WR 146 RD 155 150 149 D0-D23
Data Out Data Out Data Out
148
156
AA0473
Figure 2-15 DRAM Page Mode Write Accesses
Not Recommended for New Design
2-30 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
RAS 136 131 CAS 137 140
Row Add Column Address
135
139 141
Column Address
138 142
Last Column Address
A0-A17
143 WR 132 133 153 RD 134 154 D0-D23
Data In Data In Data In
152
AA0474
Figure 2-16 DRAM Page Mode Read Accesses
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-31
Specifications External Memory Interface (Port A)
DRAM Type (tRAC ns)
Note:
This figure should be used for primary selection. For exact and detailed timings, see the following tables.
100
80
70
60
50 40 66 80 100 120 11 Wait States 15 Wait States
Chip Frequency (MHz)
4 Wait States 8 Wait States
AA0475
Figure 2-17 DRAM Out-of-Page Wait States Selection Guide Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2
No. 157 158 159 160 161 Characteristics3 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Symbol tRC tRAC tCAC tAA tOFF Expression 5 x TC 2.75 x TC - 7.5 1.25 x TC - 7.5 1.5 x TC - 7.5 N 20 MHz4 Min 250.0 N N N 0.0 Max N 130.0 55.0 67.5 N 30 MHz4 Min 166.7 N N N 0.0 Max N 84.2 34.2 42.5 N ns ns ns ns ns Unit
Not Recommended for New Design
2-32 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued)
No. 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 Characteristics3 RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion RAS deassertion to WR assertion Symbol tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH Expression 1.75 x TC - 4.0 3.25 x TC - 4.0 1.75 x TC - 4.0 2.75 x TC - 4.0 1.25 x TC - 4.0 1.5 x TC 2 1.25 x TC 2 2.25 x TC - 4.0 1.75 x TC - 4.0 1.75 x TC - 4.0 1.25 x TC - 4.0 0.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 2 x TC - 4.0 1.5 x TC - 3.8 0.75 x TC - 3.7 0.25 x TC - 3.7 20 MHz4 Min 83.5 158.5 83.5 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 8.5 83.5 158.5 96.0 71.2 33.8 8.8 Max N N N N N 77.0 64.5 N N N N N N N N N N N 30 MHz4 Min 54.3 104.3 54.3 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 4.3 54.3 104.3 62.7 46.2 21.3 4.6 Max N N N N N 52.0 43.7 N N N N N N N N N N N ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-33
Specifications External Memory Interface (Port A)
Table 2-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (Continued)
No. 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195
Notes:
Characteristics3 CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance
1. 2. 3. 4.
Symbol tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ N N
Expression 1.5 x TC - 4.2 3 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 4.25 x TC - 4.3 2.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 3 x TC - 4.3 0.5 x TC - 4.0 1.25 x TC - 4.0 4.5 x TC - 4.0 4 x TC - 7.5 N 0.75 x TC - 0.3 0.25 x TC
20 MHz4 Min 70.8 145.8 220.5 233.2 208.2 108.5 83.5 158.5 145.7 21.0 58.5 221.0 N 0.0 37.2 N Max N N N N N N N N N N N N 192.5 N N 12.5
30 MHz4 Min 45.8 95.8 145.5 154.0 137.4 71.0 54.3 104.3 95.7 12.7 37.7 146.0 N 0.0 24.7 N Max N N N N N N N N N N N N 125.8 N N 8.3
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (see Figure 2-17).
Not Recommended for New Design
2-34 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2
No. Characteristics3 Symbol tRC tRAC Expression4 9 x TC 66 MHz: 4.75 x TC - 7.5 80 MHz: 4.75 x TC - 6.5 100 MHz: 4.75 x TC - 5.7 66 MHz: 2.25 x TC - 7.5 80 MHz: 2.25 x TC - 6.5 100 MHz: 2.25 x TC - 5.7 66 MHz: 3 x TC - 7.5 80 MHz: 3 x TC - 6.5 100 MHz: 3 x TC - 5.7 66 MHz 80 MHz 100 MHz Unit Min Max Min Max Min Max 136.4 N 112.5 N 90.0 N ns
157 Random read or write cycle time 158 RAS assertion to data valid (read)
N N N N N N N N N 0.0
64.5 N N 26.6 N N 40.0 N N N N N N N N 39.9 28.5 N N
N N N N N N N N N 0.0 36.6 67.9 36.6 55.4 24.1 29.3 19.9 49.1 30.4
N 52.9 N N 21.6 N N 31.0 N N N N N N N 33.3 23.9 N N
N N N N N N N N N 0.0 28.5 53.5 28.5 43.5 18.5 23.0 15.5 38.5 23.5
N N 41.8 N N 16.8 N N 24.3 N N N N N N 27.0 19.5 N N
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
159 CAS assertion to data valid (read)
tCAC
160 Column address valid to data valid (read)
tAA
161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width
tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP 3.25 x TC - 4.0 5.75 x TC - 4.0 3.25 x TC - 4.0 4.75 x TC - 4.0 2.25 x TC - 4.0 2.5 x TC 2 1.75 x TC 2 4.25 x TC - 4.0 2.75 x TC - 4.0
45.2 83.1 45.2 68.0 30.1 35.9 24.5 59.8 37.7
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-35
Specifications External Memory Interface (Port A)
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (Continued)
No. Characteristics3 Symbol tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH Expression4 3.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 4 x TC - 4.0 2 x TC - 3.8 1.25 x TC - 3.7 66 MHz: 0.25 x TC - 3.7 80 MHz: 0.25 x TC - 3.0 100 MHz: 0.25 x TC - 2.4 3 x TC - 4.2 5.5 x TC - 4.2 8.5 x TC - 4.5 8.75 x TC - 4.3 7.75 x TC - 4.3 4.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 66 MHz 80 MHz 100 MHz Unit Min Max Min Max Min Max 45.2 22.5 7.4 45.2 83.1 56.6 26.5 15.2 N N N N N N N N 36.6 17.9 5.4 36.6 67.9 46.0 21.2 11.9 N N N N N N N N 28.5 13.5 3.5 28.5 53.5 36.0 16.2 8.8 N N N N N N N N ns ns ns ns ns ns ns ns
171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column address not valid 176 Column address valid to RAS deassertion 177 WR deassertion to CAS assertion 178 CAS deassertion to WR5 assertion 179 RAS deassertion to WR5 assertion
0.1 N N 41.3 79.1 124.3 128.3 113.1 68.0 45.2 83.1
N N N N N N N N N N N
N 0.1 N 33.3 64.6 101.8 105.1 92.6 55.4 36.6 67.9
N N N N N N N N N N N
N N 0.1 25.8 50.8 80.5 83.2 73.2 43.5 28.5 53.5
N N N N N N N N N N N
ns ns ns ns ns ns ns ns ns ns ns
180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion 182 WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write)
tWCH tWCR tWP tRWL tCWL tDS tDH tDHR
Not Recommended for New Design
2-36 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (Continued)
No. Characteristics3 Symbol tWCS tCSR tRPC tROH tGA Expression4 5.5 x TC - 4.3 1.5 x TC - 4.0 1.75 x TC - 4.0 8.5 x TC - 4.0 66 MHz: 7.5 x TC - 7.5 80 MHz: 7.5 x TC - 6.5 100 MHz: 7.5 x TC - 5.7 0.0 0.75 x TC - 0.3 0.25 x TC 66 MHz 80 MHz 100 MHz Unit Min Max Min Max Min Max 79.0 18.7 22.5 124.8 N N N N 64.5 14.8 17.9 102.3 N N N N 50.7 11.0 13.5 81.0 N N N N ns ns ns ns
188 WR assertion to CAS assertion 189 CAS assertion to RAS assertion (refresh) 190 RAS deassertion to CAS assertion (refresh) 191 RD assertion to RAS deassertion 192 RD assertion to data valid
N N N 0.0 11.1 N
106.1 N N N N 3.8
N N N 0.0 9.1 N
N 87.3 N N N 3.1
N N N 0.0 7.2 N
N N 69.3 N N 2.5
ns ns ns ns ns ns
193 RD deassertion to data not valid3 194 WR assertion to data active 195 WR deassertion to data high impedance
Notes: 1. 2. 3. 4. 5.
tGZ N N
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. The asynchronous delays specified in the expressions are valid for DSP56307. Either tRCH or tRRH must be satisfied for read cycles.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-37
Specifications External Memory Interface (Port A)
Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2
No. Characteristics3 Symbol tRC tRAC Expression4 12 x TC 66 MHz: 6.25 x TC - 7.5 80 MHz: 6.25 x TC - 6.5 100 MHz: 6.25 x TC - 5.7 66 MHz: 3.75 x TC - 7.5 80 MHz: 3.75 x TC - 6.5 100 MHz: 3.75 x TC - 5.7 66 MHz: 4.5 x TC - 7.5 80 MHz: 4.5 x TC - 6.5 100 MHz: 4.5 x TC - 5.7 66 MHz 80 MHz 100 MHz Unit Min Max Min Max Min Max 181.8 N 150.0 N 120.0 N ns
157 Random read or write cycle time 158 RAS assertion to data valid (read)
N N N N N N N N N 0.0
87.2 N N 49.3 N N 60.7 N N N N N N N N 39.9 28.5 N N
N N N N N N N N N 0.0 49.1 92.9 61.6 74.1 42.9 29.3 19.9 67.9 49.1
N 71.6 N N 40.4 N N 49.8 N N N N N N N 33.3 23.9 N N
N N N N N N N N N 0.0 38.5 73.5 48.5 58.5 33.5 23.0 15.5 53.5 38.5
N N 56.8 N N 31.8 N N 39.3 N N N N N N 27.0 19.5 N N
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
159 CAS assertion to data valid (read)
tCAC
160 Column address valid to data valid (read)
tAA
161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width
tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP 4.25 x TC - 4.0 7.75 x TC - 4.0 5.25 x TC - 4.0 6.25 x TC - 4.0 3.75 x TC - 4.0 2.5 x TC 2 1.75 x TC 2 5.75 x TC - 4.0 4.25 x TC - 4.0
60.4 113.4 75.5 90.7 52.8 35.9 24.5 83.1 60.4
Not Recommended for New Design
2-38 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued)
No. Characteristics3 Symbol tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH Expression4 4.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6 x TC - 4.0 3.0 x TC - 3.8 1.75 x TC - 3.7 66 MHz: 0.25 x TC - 3.7 80 MHz: 0.25 x TC - 3.0 100 MHz: 0.25 x TC - 2.4 5 x TC - 4.2 7.5 x TC - 4.2 11.5 x TC - 4.5 11.75 x TC - 4.3 10.25 x TC - 4.3 5.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 66 MHz 80 MHz 100 MHz Unit Min Max Min Max Min Max 60.4 22.5 7.4 75.5 113.4 86.9 41.7 22.8 N N N N N N N N 49.1 17.9 5.4 61.6 92.9 71.0 33.7 18.2 N N N N N N N N 38.5 13.5 3.5 48.5 73.5 56.0 26.2 13.8 N N N N N N N N ns ns ns ns ns ns ns ns
171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column address not valid 176 Column address valid to RAS deassertion 177 WR deassertion to CAS assertion 178 CAS deassertion to WR5 assertion 179 RAS deassertion to WR5 assertion
0.1 N N 71.6 109.4 169.7 173.7 151.0 83.1 75.5 113.4
N N N N N N N N N N N
N 0.1 N 58.3 89.6 139.3 142.7 130.1 67.9 61.6 92.9
N N N N N N N N N N N
N N 0.1 45.8 70.8 110.5 113.2 103.2 53.5 48.5 73.5
N N N N N N N N N N N
ns ns ns ns ns ns ns ns ns ns ns
180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion 182 WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion 185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write) 187 RAS assertion to data not valid (write)
tWCH tWCR tWP tRWL tCWL tDS tDH tDHR
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-39
Specifications External Memory Interface (Port A)
Table 2-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued)
No. Characteristics3 Symbol tWCS tCSR tRPC tROH tGA Expression4 6.5 x TC - 4.3 1.5 x TC - 4.0 2.75 x TC - 4.0 11.5 x TC - 4.0 66 MHz: 10 x TC - 7.5 80 MHz: 10 x TC - 6.5 100 MHz: 10 x TC - 5.7 N 0.75 x TC - 0.3 0.25 x TC 66 MHz 80 MHz 100 MHz Unit Min Max Min Max Min Max 94.2 18.7 37.7 170.2 N N N N 77.0 14.8 30.4 139.8 N N N N 60.7 11.0 23.5 111.0 N N N N ns ns ns ns
188 WR assertion to CAS assertion 189 CAS assertion to RAS assertion (refresh) 190 RAS deassertion to CAS assertion (refresh) 191 RD assertion to RAS deassertion 192 RD assertion to data valid
N N N 0.0 11.1 N
144.0 N N N N 3.8
N N N 0.0 9.1 N
N 118.5 N N N 3.1
N N N 0.0 7.2 N
N N 94.3 N N 2.5
ns ns ns ns ns ns
193 RD deassertion to data not valid3 194 WR assertion to data active 195 WR deassertion to data high impedance
Notes: 1. 2. 3. 4. 5.
tGZ N N
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. The asynchronous delays specified in the expressions are valid for DSP56307. Either tRCH or tRRH must be satisfied for read cycles.
Not Recommended for New Design
2-40 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2
No. Characteristics3 66 MHz Symbol tRC tRAC Expression Min Max Min Max Min Max 16 x TC 66 MHz: 8.25 x TC - 7.5 80 MHz: 8.25 x TC - 6.5 100 MHz: 8.25 x TC - 5.7 66 MHz: 4.75 x TC - 7.5 80 MHz: 4.75 x TC - 6.5 100 MHz: 4.75 x TC - 5.7 66 MHz: 5.5 x TC - 7.5 80 MHz: 5.5 x TC - 6.5 100 MHz: 5.5 x TC - 5.7 0.0 6.25 x TC - 4.0 9.75 x TC - 4.0 6.25 x TC - 4.0 8.25 x TC - 4.0 4.75 x TC - 4.0 3.5 x TC 2 2.75 x TC 2 7.75 x TC - 4.0 6.25 x TC - 4.0 242.4 N 200.0 N 160.0 N ns 80 MHz 100 MHz Unit
157 Random read or write cycle time 158 RAS assertion to data valid (read)
N N N N N N N N N 0.0 90.7 143.7 90.7 121.0 68.0 51.0 39.7 113.4 90.7
117.5 N N 64.5 N N 75.8 N N N N N N N N 55.0 43.7 N N
N N N N N N N N N 0.0 74.1 117.9 74.1 99.1 55.4 41.8 32.4 92.9 74.1
N 96.6 N N 52.9 N N 62.3 N N N N N N N 45.8 36.4 N N
N N N N N N N N N 0.0 58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5 58.5
N N 76.8 N N 41.8 N N 49.3 N N N N N N 37.0 29.5 N N
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
159 CAS assertion to data valid (read)
tCAC
160 Column address valid to data valid (read)
tAA
161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion 165 RAS assertion to CAS deassertion 166 CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width
tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-41
Specifications External Memory Interface (Port A)
Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (Continued)
No. Characteristics3 66 MHz Symbol tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH Expression Min Max Min Max Min Max 6.25 x TC - 4.0 2.75 x TC - 4.0 0.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 7 x TC - 4.0 5 x TC - 3.8 1.75 x TC - 3.7 66 MHz: 0.25 x TC - 3.7 80 MHz: 0.25 x TC - 3.0 100 MHz: 0.25 x TC - 2.4 6 x TC - 4.2 9.5 x TC - 4.2 15.5 x TC - 4.5 90.7 37.7 7.4 90.7 143.7 102.1 72.0 22.8 N N N N N N N N 74.1 30.4 5.4 74.1 117.9 83.5 58.7 18.2 N N N N N N N N 58.5 23.5 3.5 58.5 93.5 66.0 46.2 13.8 N N N N N N N N ns ns ns ns ns ns ns ns 80 MHz 100 MHz Unit
171 Row address valid to RAS assertion 172 RAS assertion to row address not valid 173 Column address valid to CAS assertion 174 CAS assertion to column address not valid 175 RAS assertion to column address not valid 176 Column address valid to RAS deassertion 177 WR deassertion to CAS assertion 178 CAS deassertion to WR assertion4 179 RAS deassertion to WR assertion4
0.1 N N 86.7 139.7 230.3
N N N N N N N
N 0.1 N 70.8 114.6 189.3 192.6
N N N N N N N
N N 0.1 55.8 90.8 150.5 153.2
N N N N N N N
ns ns ns ns ns ns ns
180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion 182 WR assertion pulse width 183 WR assertion to RAS deassertion 184 WR assertion to CAS deassertion
tWCH tWCR tWP tRWL tCWL
15.75 x TC - 4.3 234.3 6680 MHz: 14.25 x TC - 4.3 211.6 100 MHz: 14.75 x TC - 4.3 N 8.75 x TC - 4.0 6.25 x TC - 4.0 128.6 90.7
N N N N
180.1 N 105.4 74.1
N N N N
N 143.2 83.5 58.5
N N N N
ns ns ns ns
185 Data valid to CAS assertion (write) 186 CAS assertion to data not valid (write)
tDS tDH
Not Recommended for New Design
2-42 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Table 2-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (Continued)
No. Characteristics3 66 MHz Symbol tDHR tWCS tCSR tRPC tROH tGA Expression Min Max Min Max Min Max 9.75 x TC - 4.0 9.5 x TC - 4.3 1.5 x TC - 4.0 4.75 x TC - 4.0 15.5 x TC - 4.0 66 MHz: 14 x TC - 7.5 80 MHz: 14 x TC - 6.5 100 MHz: 14 x TC - 5.7 N 0.75 x TC - 0.3 0.25 x TC 143.7 139.6 18.7 68.0 230.8 N N N N N 117.9 114.5 14.8 55.4 189.8 N N N N N 93.5 90.7 11.0 43.5 151.0 N N N N N ns ns ns ns ns 80 MHz 100 MHz Unit
187 RAS assertion to data not valid (write) 188 WR assertion to CAS assertion 189 CAS assertion to RAS assertion (refresh) 190 RAS deassertion to CAS assertion (refresh) 191 RD assertion to RAS deassertion 192 RD assertion to data valid
N N N 0.0 11.1 N
204.6 N N N N 3.8
N N N 0.0 9.1 N
N 168.5 N N N 3.1
N N N 0.0 7.2 N
N N 134.3 N N 2.5
ns ns ns ns ns ns
193 RD deassertion to data not valid3 194 WR assertion to data active 195 WR deassertion to data high impedance
Notes: 1. 2. 3. 4.
tGZ N N
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-43
Specifications External Memory Interface (Port A)
157 162 RAS 167 169 168 170 CAS 171 173 174 175 A0-A17
Row Address Column Address
163 165
162
164
166
172 177 191 WR 160 159 RD 158 192
176 179
168
193
161
Data In
D0-D23
AA0476
Figure 2-18 DRAM Out-of-Page Read Access
Not Recommended for New Design
2-44 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
157 162 163 165 162
RAS 167 169 168 170 CAS 171 173 172
164
166
174 176
A0-A17
Row Address 181
Column Address
175 188 WR 182 180
184 183 RD
187 186 185 194 195
D0-D23
Data Out
AA0477
Figure 2-19 DRAM Out-of-Page Write Access
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-45
Specifications External Memory Interface (Port A)
157 162 RAS 190 170 CAS 165 163 162
189 177 WR
AA0478
Figure 2-20 DRAM Refresh Access
Not Recommended for New Design
2-46 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
Synchronous Timings
Table 2-17 External Bus Synchronous Timings1
No. Characteristics Expression2,3 0.25 x TC + 4.0 0.25 x TC N N 0.25 x TC 0.25 x TC + 4.0 0.25 x TC 0.25 x TC N N 0.75 x TC + 4.0 N For WS = 1 or WS 4 0.5 x TC + 4.3 For 2 WS 3 N 100 MHz4 Unit Min N 2.5 4.0 0.0 2.5 3.3 2.5 N 4.0 0.0 8.2 0.0 6.3 1.3 0.0 Max 6.5 N N N N 6.5 N 2.5 N N 11.5 4.0 9.3 4.3 3.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
198 CLKOUT high to address, and AA valid5 199 CLKOUT high to address, and AA invalid5 200 TA valid to CLKOUT high (setup time) 201 CLKOUT high to TA invalid (hold time) 202 CLKOUT high to data out active 203 CLKOUT high to data out valid 204 CLKOUT high to data out invalid 205 CLKOUT high to data out high impedance 206 Data in valid to CLKOUT high (setup) 207 CLKOUT high to data in invalid (hold) 208 CLKOUT high to RD assertion 209 CLKOUT high to RD deassertion 210 CLKOUT high to WR 100 MHz All frequencies assertion6
211 CLKOUT high to WR deassertion
Notes: 1. 2. 3. 4. 5.
6.
External bus synchronous timings should be used only for reference to the clock and not for relative timings. WS is the number of wait states specified in the BCR. The asynchronous delays specified in the expressions are valid for DSP56307. For operation at greater than 80MHz, we recommend that you set the asynchronous bus enable bit (ABE) in the OMR to activate asynchronous bus arbitration. T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to determine whether the access referenced by A0A23 is internal or external, when this mode is enabled If WS > 1, WR assertion refers to the next rising edge of CLKOUT.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-47
Specifications External Memory Interface (Port A)
CLKOUT 198 A0-A17 AA0-AA3 201 200 TA 211 WR 210 203 D0-D23 202 208 RD 207 206 D0-D23 Data In
AA0479
199
205 204 Data Out
209
Figure 2-21 Synchronous Bus Timings 1 WS (BCR Controlled)
Not Recommended for New Design
2-48 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
CLKOUT 198 A0-A17 AA0-AA3 201 200 TA 211 WR 210 203 D0-D23 202 208 RD 207 206 D0-D23 Data In
AA1615
199
201 200
205 204 Data Out
209
Figure 2-22 Synchronous Bus Timings, SRAM, 2 or More WS, TA Controlled
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-49
Specifications External Memory Interface (Port A)
Arbitration Timings
Table 2-18 Arbitration Bus Timings1
100 MHz No. Characteristics Expression Min Max 212 CLKOUT high to BR assertion/deassertion2 213 BG asserted/deasserted to CLKOUT high (setup)3 214 CLKOUT high to BG deasserted/asserted 215 BB deassertion to CLKOUT high (input 216 CLKOUT high to BB assertion (input 217 CLKOUT high to BB assertion (output) 218 CLKOUT high to BB deassertion (output) 219 BB high to BB high impedance (output) 220 CLKOUT high to address and controls active 221 CLKOUT high to address and controls high impedance 222 CLKOUT high to AA active 223 CLKOUT high to AA deassertion4 224 CLKOUT high to AA high impedance 225 BG deassertion to BB assertion (output)5 226 BB (input) assertion to BG
Notes: 1. 2. 3. 4. 5.
Unit 1.0 4.0 0.0 4.0 0.0 1.0 1.0 N 2.5 N 2.5 3.2 N N 25 4.0 N N N N 4.0 4.0 4.5 N 2.5 N 6.5 7.5 30 N ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
N N N N N N N N 0.25 x TC 0.25 x TC 0.25 x TC 0.25 x TC + 4.0 0.75 x TC 2.5 x TC + 5 2 x TC + 5
(hold)3
setup)3
hold)3
assertion5
The asynchronous delays specified in the expressions are valid for DSP56307. T212 is valid for address trace mode when the ATE bit (Bit 15) in the OMR is set. BR is deasserted for internal accesses and asserted for external accesses. T213, T214, T215, and T216 are valid only when the ABE bit (Bit 13) in the OMR is cleared. When an expression appears with both a minimum and maximum value, use the expression to calculate worst case. Asynchronous bus arbitration mode inserts a delay between changes in BG and BB until the change is actually OseenO by the chip internally (i.e., this delay is required because internal chip operation is synchronous). T225 and T226 are valid for asynchronous bus arbitration mode only (i.e., when the ABE bit in the OMR is set). If ABE is set, T213, T214, T215, and T216 are not required for proper operation, and BG and BB do not have setup and input hold requirements with respect to CLKOUT. The delay between the deassertion of BG for a DSP56307 and the assertion of a second BG to another DSP56307 must be greater than the sum of T225 (for the first chip) and T226 (for the second chip) to prevent bus access by more than one DSP at a time.
Not Recommended for New Design
2-50 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
CLKOUT 212 BR 214 213 BG 216 215 BB 220 A0-A17 RD, WR 222 AA0-AA3
AA0481
217
Figure 2-23 Bus Acquisition Timings
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-51
Specifications External Memory Interface (Port A)
CLKOUT 212 BR 214 213 BG 219 218 BB 221 A0-A17 RD, WR 224 223 AA0-AA3
AA0482
Figure 2-24 Bus Release Timings Case 1 (BRT Bit in OMR Cleared)
Not Recommended for New Design
2-52 DSP56307 Technical Data MOTOROLA
Specifications External Memory Interface (Port A)
CLKOUT 212 BR 214 213 BG 219 218 BB 221 A0-A17 RD, WR 224 223 AA0-AA3
AA0483
Figure 2-25 Bus Release Timings Case 2 (BRT Bit in OMR Set)
BG
225 BB
(output)
AA1417
Figure 2-26 Bus Arbitration Mode Timing for Assuming Bus Mastership (ABE Bit in OMR Set)
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-53
Specifications Host Interface Timing
BG
226
BB (input)
AA1426
Figure 2-27 Bus Arbitration Mode Timing for Issuing a New BG Signal (ABE Bit in OMR Set)
HOST INTERFACE TIMING
Table 2-19 Host Interface Timing1, 2
No. Characteristic3 100 MHz Expression Min Max TC + 9.9 N 19.9 9.9 31.6 N N N ns ns ns Unit
317 Read data strobe assertion width4 HACK assertion width 318 Read data strobe deassertion width4 HACK deassertion width
319 Read data strobe deassertion width4 after OLast Data 2.5 x TC + 6.6 RegisterO reads5,6, or between two consecutive CVR, ICR, or ISR reads7 HACK deassertion width after OLast Data RegisterO reads5,6 320 Write data strobe assertion width8 width8 N 321 Write data strobe deassertion 2.5 x TC + 6.6 HACK write deassertion width: after HcTR, HCVR, and OLast Data Register 2.5 x TC + 8.3 Writes after TXH:TXM writes (with HBE=0), 2.5 x TC + 6.6 TXM:TXL writes (with HBE=1) 322 HAS assertion width 323 HAS deassertion to data strobe assertion9 N N N N
13.2 31.6 39.5 31.6
N N
ns
@80 MHz @100 MHz @80 MHz @100 MHz N N N N ns ns ns ns
9.9 0.0 9.9 3.3
324 Host data input setup time before write data strobe deassertion8 325 Host data input hold time after write data strobe deassertion8
Not Recommended for New Design
2-54 DSP56307 Technical Data MOTOROLA
Specifications Host Interface Timing
Table 2-19 Host Interface Timing1, 2 (Continued)
No. Characteristic3 100 MHz Expression Min Max N 3.3 N ns Unit
326 Read data strobe assertion to output data active from high impedance4 HACK assertion to output data active from high impedance 327 Read data strobe assertion to output data valid4 HACK assertion to output data valid 328 Read data strobe deassertion to output data high impedance4 HACK deassertion to output data high impedance 329 Output data hold time after read data strobe deassertion4 Output data hold time after HACK deassertion 330 HCS assertion to read data strobe deassertion4 331 HCS assertion to write data strobe deassertion8 332 HCS assertion to output data valid 333 HCS hold time after data strobe deassertion9 334 Address (HAD0HAD7) setup time before HAS deassertion (HMUX=1) 335 Address (HAD0HAD7) hold time after HAS deassertion (HMUX=1) 336 HA8HA10 (HMUX=1), HA0HA2 (HMUX=0), HR/W setup time before data strobe assertion9 Read Write 337 HA8HA10 (HMUX=1), HA0HA2 (HMUX=0), HR/W hold time after data strobe deassertion9
N N
N N
23.54 9.9
ns ns
N
4.1
N
ns
TC + 9.9 N N N N N N
19.9 9.9 N 0.0 4.7 3.3
N N 16.5 N N N
ns ns ns ns ns ns
0 4.7 N 3.3 36.5 31.5 N
N N N N N 20.24
ns ns ns ns ns ns
338 Delay from read data strobe deassertion to host 2 x TC + 20.6 request assertion for OLast Data RegisterO read4, 5, 10 339 Delay from write data strobe deassertion to host 1.5 x TC + 16.5 request assertion for OLast Data RegisterO write5, 8, 10 340 Delay from data strobe assertion to host request deassertion for OLast Data RegisterO read or write (HROD=0)5, 9, 10 341 Delay from data strobe assertion to host request deassertion for OLast Data RegisterO read or write (HROD=1, open drain host request)5, 9, 10, 11 N
N
N
300.0
ns
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-55
Specifications Host Interface Timing
Table 2-19 Host Interface Timing1, 2 (Continued)
No.
Notes: 1. 2.
Characteristic3
100 MHz Expression Min Max Unit
See Host Port Usage Considerations in the DSP56307 User's Manual. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. 3. VCCQL = 2.5 V 0.25 V; TJ = -40uC to +100 uC, CL = 50 pF 4. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode. 5. The Olast data registerO is the register at address $7, which is the last location to be read or written in data transfers. This is RXL/TXL in the little endian mode (HBE = 0), or RXH/TXH in the big endian mode (HBE = 1). 6. This timing is applicable only if a read from the Olast data registerO is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal. 7. This timing is applicable only if two consecutive reads from one of these registers are executed. 8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode 10. The host request is HREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 11. In this calculation, the host request signal is pulled up by a 4.7 k resistor in the open-drain mode.
317 HACK 327 326 H0-H7 329 328
318
HREQ
AA1105
Figure 2-28 Host Interrupt Vector Register (IVR) Read Timing Diagram
Not Recommended for New Design
2-56 DSP56307 Technical Data MOTOROLA
Specifications Host Interface Timing
HA0-HA2 336 330 HCS 337 333
317 HRD, HDS 318 328 332 327 326 H0-H7 340 341 HREQ, HRRQ, HTRQ 338 319 329
AA0484G
Figure 2-29 Read Timing Diagram, Non-Multiplexed Bus
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-57
Specifications Host Interface Timing
HA0-HA2 336 331 333 HCS 337
320 HWR, HDS 321 324 325 H0-H7 340 341 HREQ, HRRQ, HTRQ
AA0485G
339
Figure 2-30 Write Timing Diagram, Non-Multiplexed Bus
Not Recommended for New Design
2-58 DSP56307 Technical Data MOTOROLA
Specifications Host Interface Timing
HA8-HA10 336 322 HAS 323 337
317 HRD, HDS 334 335 327 328 329 HAD0-HAD7 Address 326 340 341 HREQ, HRRQ, HTRQ
AA0486G
318 319
Data
338
Figure 2-31 Read Timing Diagram, Multiplexed Bus
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-59
Specifications Host Interface Timing
HA8-HA10 336
322 HAS
323
320 HWR, HDS 334 335 HAD0-HAD7 Address Data 340 341 HREQ, HRRQ, HTRQ
AA0487G
324
321 325
339
Figure 2-32 Write Timing Diagram, Multiplexed Bus
Not Recommended for New Design
2-60 DSP56307 Technical Data MOTOROLA
Specifications SCI Timing
SCI TIMING
Table 2-20 SCI Timing
No. Characteristics1 100 MHz Symbol tSCC2 N N N N N N N N N N tACC3 N N N N 64 x TC tACC/2 - 10.0 tACC/2 - 10.0 tACC/2 - 30.0 tACC/2 - 30.0 TC + 8.0 N N 8 x TC tSCC/2 - 10.0 tSCC/2 - 10.0 tSCC/4 + 0.5 x TC -17.0 tSCC/4 - 0.5 x TC tSCC/4 + 0.5 x TC + 25.0 tSCC/4 + 0.5 x TC - 5.5 N Expression Min Max 80.0 30.0 30.0 8.0 15.0 50.0 N N 18.0 0.0 9.0 640.0 310.0 310.0 290.0 290.0 N N N N N N 19.5 32.0 N N N N N N N N ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
400 Synchronous clock cycle 401 Clock low period 402 Clock high period 403 Output data setup to clock falling edge (internal clock) 404 Output data hold after clock rising edge (internal clock) 405 Input data setup time before clock rising edge (internal clock) 406 Input data not valid before clock rising edge (internal clock) 407 Clock falling edge to output data valid (external clock) 408 Output data hold after clock rising edge (external clock) 409 Input data setup time before clock rising edge (external clock) 410 Input data hold time after clock rising edge (external clock) 411 Asynchronous clock cycle 412 Clock low period 413 Clock high period 414 Output data setup to clock rising edge (internal clock) 415 Output data hold after clock rising edge (internal clock)
Notes: 1. 2. 3.
VCCQL = 2.5 V 0.25 V; TJ = -40uC to +100 uC, CL = 50 pF tSCC = synchronous clock cycle time (For internal clock, tSCC is determined by the SCI clock control register and TC.) tACC = asynchronous clock cycle time; value given for 1x Clock mode (For internal clock, tACC is determined by the SCI clock control register and TC.)
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-61
Specifications SCI Timing
400 401 SCLK (Output) 403 TXD
Data Valid
402
404
405 406 RXD
Data Valid
a) Internal Clock
400 401 SCLK (Input) 407 TXD
Data Valid
402
408
409 RXD
Data Valid
410
b) External Clock
AA0488
Figure 2-33 SCI Synchronous Mode Timing
411 412 1X SCLK (Output) 414 TXD
Data Valid
413
415
AA0489
Figure 2-34 SCI Asynchronous Mode Timing
Not Recommended for New Design
2-62 DSP56307 Technical Data MOTOROLA
Specifications ESSI0/ESSI1 Timing
ESSI0/ESSI1 TIMING
Table 2-21 ESSI Timings
No. Characteristics1, 2, 3 Symbol tSSICC N Expression 3 x TC 4 x TC 2 x TC - 10.0 1.5 x TC 2 x TC - 10.0 1.5 x TC N N N N N N N N N N N N N 100 MHz Cond4 Unit Min Max ition 30.0 40.0 10.0 15.0 10.0 15.0 N N N N N N N N N N N N 0.0 19.0 5.0 3.0 23.0 1.0 23.0 1.0 3.0 0.0 0.0 19.0 6.0 0.0 N N N N N N 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 N N N N N N N N N N N N N N x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a
x ck i ck s
430 Clock cycle5 431 Clock high period For internal clock For external clock 432 Clock low period For internal clock For external clock 433 RXC rising edge to FSR out (bl) high 434 RXC rising edge to FSR out (bl) low 435 RXC rising edge to FSR out (wr) high6 436 RXC rising edge to FSR out (wr) low6 437 RXC rising edge to FSR out (wl) high 438 RXC rising edge to FSR out (wl) low 439 Data in setup time before RXC (SCK in Synchronous mode) falling edge 440 Data in hold time after RXC falling edge 441 FSR input (bl, wr) high before RXC falling edge6 442 FSR input (wl) high before RXC falling edge 443 FSR input hold time after RXC falling edge 444 Flags input setup before RXC falling edge 445 Flags input hold time after RXC falling edge
x ck i ck
ns
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ns
N
N N N N N N N N N N N N N
x ck i ck s
ns
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-63
Specifications ESSI0/ESSI1 Timing
Table 2-21 ESSI Timings (Continued)
No. Characteristics1, 2, 3 Symbol N N N N N N N N N N N N N N N N N Expression N N N N N N N N 35 + 0.5 x TC 21.0 N N N N N N N N 100 MHz Cond4 Unit Min Max ition N N N N N N N N N N N N N N N N N N N N N N 2.0 21.0 N N 2.0 21.0 4.0 0.0 N N 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 40.0 21.0 31.0 16.0 34.0 20.0 N N 27.0 31.0 N N N N 32.0 18.0 x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck
--
446 TXC rising edge to FST out (bl) high 447 TXC rising edge to FST out (bl) low 448 TXC rising edge to FST out (wr) high6 449 TXC rising edge to FST out (wr) low6 450 TXC rising edge to FST out (wl) high 451 TXC rising edge to FST out (wl) low 452 TXC rising edge to data out enable from high impedance 453 TXC rising edge to Transmitter #0 drive enable assertion 454 TXC rising edge to data out valid 455 TXC rising edge to data out high impedance7 456 TXC rising edge to Transmitter #0 drive enable deassertion7 457 FST input (bl, wr) setup time before TXC falling edge6 458 FST input (wl) to data out enable from high impedance 459 FST input (wl) to Transmitter #0 drive enable assertion 460 FST input (wl) setup time before TXC falling edge 461 FST input hold time after TXC falling edge 462 Flag output valid after TXC rising edge
ns ns ns ns ns ns ns ns ns ns ns ns
ns
N x ck i ck x ck i ck x ck i ck
ns ns ns ns
Not Recommended for New Design
2-64 DSP56307 Technical Data MOTOROLA
Specifications ESSI0/ESSI1 Timing
Table 2-21 ESSI Timings (Continued)
No.
Notes: 1. 2.
Characteristics1, 2, 3
Symbol
Expression
100 MHz Cond4 Unit Min Max ition
3.
4.
5. 6.
7.
VCCQL = 2.5 V 0.25 V; TJ = -40uC to +100 uC, CL = 50 pF i ck = Internal Clock x ck = External Clock i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that TXC and RXC are two different clocks) i ck s = Internal Clock, Synchronous Mode (Synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length wr = word length relative TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) Receive Frame Sync For the internal clock, the external clock cycle is defined by Icyc and the ESSI control register. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as Bit Length Frame Sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-65
Specifications ESSI0/ESSI1 Timing
430
TXC (Input/ Output) FST (Bit) Out
431
432
446
447
450
451
FST (Word) Out
454 452 454 455 First Bit 459 Last Bit
Data Out Transmitter #0 Drive Enable
457 461
453
456
FST (Bit) In
458 460 461
FST (Word) In
462 See Note
Flags Out Note: In Network mode, output flag transitions can occur at the start of each time slot within the frame. In Normal mode, the output flag state is asserted for the entire frame period. AA0490
Figure 2-35 ESSI Transmitter Timing
Not Recommended for New Design
2-66 DSP56307 Technical Data MOTOROLA
Specifications ESSI0/ESSI1 Timing
430 431
RXC (Input/ Output)
433
432
434
FSR (Bit) Out
437 438
FSR (Word) Out
439
440
Data In
441 443
First Bit
Last Bit
FSR (Bit) In
442 443
FSR (Word) In
444 445
Flags In
AA0491
Figure 2-36 ESSI Receiver Timing
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-67
Specifications Timer Timing
TIMER TIMING
Table 2-22 Timer Timing
100 MHz No. 480 TIO Low 481 TIO High 482 Timer setup time from TIO (Input) assertion to CLKOUT rising edge Characteristics Expression Min 2 x TC + 2.0 2 x TC + 2.0 N 22.0 22.0 9.0 103.5 Max N N 10.0 N ns ns ns ns Unit
483 Synchronous timer delay time from CLKOUT 10.25 x TC + 1.0 rising edge to the external memory access address out valid caused by first interrupt instruction execution 484 CLKOUT rising edge to TIO (Output) assertion Minimum Maximum 0.5 x TC + 3.5 0.5 x TC + 19.8
8.5 N 8.5 N
N 24.8 N 24.8
ns ns ns ns
485 CLKOUT rising edge to TIO (Output) deassertion Minimum 0.5 x TC + 3.5 Maximum 0.5 x TC + 19.0
Note: VCCQL = 2.5 V 0.25 V; TJ = 40uC to +100 uC, CL = 50 pF
TIO 480 481
AA0492
Figure 2-37 TIO Timer Event Input Restrictions
CLKOUT
TIO (Input) 482
Address 483 First Interrupt Instruction Execution
AA0493
Figure 2-38 Timer Interrupt Generation
Not Recommended for New Design
2-68 DSP56307 Technical Data MOTOROLA
Specifications Timer Timing
CLKOUT
TIO (Output) 484 485
AA0494
Figure 2-39 External Pulse Generation
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-69
Specifications GPIO Timing
GPIO TIMING
Table 2-23 GPIO Timing
100 MHz No. 490 491 492 493 494
Note:
Characteristics CLKOUT edge to GPIO out valid (GPIO out delay time) CLKOUT edge to GPIO out not valid (GPIO out hold time) GPIO In valid to CLKOUT edge (GPIO in set-up time) CLKOUT edge to GPIO in not valid (GPIO in hold time) Fetch to CLKOUT edge before GPIO change
Expression Min N N N N 6.75 x TC N 3.0 12.0 0.0 67.5 Max 31.0 N N N N
Unit ns ns ns ns ns
VCCQL = 2.5 V 0.25 V; TJ = -40uC to +100 uC, CL = 50 pF
CLKOUT (Output) 490 491 GPIO (Output) 492 GPIO (Input) Valid 493
A0-A17 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register.
AA0495
Figure 2-40 GPIO Timing
Not Recommended for New Design
2-70 DSP56307 Technical Data MOTOROLA
Specifications JTAG Timing
JTAG TIMING
Table 2-24 JTAG Timing
All frequencies No. Characteristics Min 500 TCK frequency of operation (1/(TC x 3); maximum 22 MHz) 501 TCK cycle time in Crystal mode 502 TCK clock pulse width measured at 1.5 V 503 TCK rise and fall times 504 Boundary scan input data setup time 505 Boundary scan input data hold time 506 TCK low to output data valid 507 TCK low to output high impedance 508 TMS, TDI data setup time 509 TMS, TDI data hold time 510 TCK low to TDO data valid 511 TCK low to TDO high impedance 512 TRST assert time 513 TRST setup time to TCK low
Notes: 1. 2.
Unit Max 22.0 N N 3.0 N N 40.0 40.0 N N 44.0 44.0 N N MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0 25.0 0.0 0.0 100.0 40.0
VCCQL = 2.5 V 0.25 V; TJ = -40uC to +100 uC, CL = 50 pF All timings apply to OnCE module data transfers, because it uses the JTAG port as an interface.
501 502 TCK (Input)
VIH VIL VM
502
VM
503
503
AA0496
Figure 2-41 Test Clock Input Timing Diagram
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-71
Specifications JTAG Timing
TCK (Input)
VIL 504
VIH 505
Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid
AA0497
Figure 2-42 Boundary Scan (JTAG) Timing Diagram
TCK (Input) TDI TMS (Input) 510 TDO (Output) 511 TDO (Output) 510 TDO (Output) Output Data Valid
AA0498
VIH VIL 508 Input Data Valid 509
Output Data Valid
Figure 2-43 Test Access Port Timing Diagram
Not Recommended for New Design
2-72 DSP56307 Technical Data MOTOROLA
Specifications OnCE Module TimIng
TCK (Input) 513 TRST (Input) 512
AA0499
Figure 2-44 TRST Timing Diagram
OnCE MODULE TIMING
Table 2-25 OnCE Module Timing
100 MHz No. Characteristics Expression Min Max 500 TCK frequency of operation 514 DE assertion time in order to enter Debug mode 515 Response time when DSP56307 is executing NOP instructions from internal memory 516 Debug acknowledge assertion time
Note:
Unit 0.0 25.0 N 40.0 22.0 MHz N 85.0 N ns ns ns
1/(TC x 3), max 22.0 MHz 1.5 x TC + 10.0 5.5 x TC + 30.0 3 x TC + 10.0
VCCQL = 2.5 V 0.25 V; TJ = -40uC to +100 uC, CL = 50 pF
DE 514 515 516
AA0500
Figure 2-45 OnCENDebug Request
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 2-73
Specifications OnCE Module TimIng
Not Recommended for New Design
2-74 DSP56307 Technical Data MOTOROLA
SECTION 3 PACKAGING
PIN-OUT AND PACKAGE INFORMATION
This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for the package. The DSP56307 is available in a 196-pin Plastic Ball Grid Array (PBGA) package.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 3-1
Packaging Pin-out and Package Information
PBGA Package Description
Top and bottom views of the PBGA package are shown in Figure 3-1 and Figure 3-2 with their pin-outs.
Top View
1 A NC 2 SC11 3 TMS 4 TDO 5 IRQB 6 D23 7 VCCD 8 D19 9 D16 10 D14 11 D11 12 D9 13 D7 14 NC
B
SRD1
SC12
TDI
TRST
IRQD
D21
D20
D17
D15
D13
D10
D8
D5
NC
C
SC02
STD1
TCK
IRQA
IRQC
D22
VCCQL
D18
VCCD
D12
VCCD
D6
D3
D4
D
PINIT
SC01
DE
GND
GND
GND
GND
GND
GND
GND
GND
D1
D2
VCCD
E
STD0
VCCS
SRD0
GND
GND
GND
GND
GND
GND
GND
GND
A17
A16
D0
F
RXD
SC10
SC00
GND
GND
GND
GND
GND
GND
GND
GND
VCCQH
A14
A15
G
SCK1
SCLK
TXD
GND
GND
GND
GND
GND
GND
GND
GND
A13
VCCQL
A12
H
VCCQH
VCCQL
SCK0
GND
GND
GND
GND
GND
GND
GND
GND
VCCA
A10
A11
J
HACK
HRW
HDS
GND
GND
GND
GND
GND
GND
GND
GND
A8
A7
A9
K
VCCS
HREQ
TIO2
GND
GND
GND
GND
GND
GND
GND
GND
VCCA
A5
A6
L
HCS
TIO1
TIO0
GND
GND
GND
GND
GND
GND
GND
GND
VCCA
A3
A4
M
HA1
HA2
HA0
VCCH
PB0
VCCP
VCCQH
EXTAL
CLK OUT
BCLK
WR
RD
A1
A2
N
H6
H7
H4
H2
RESET GNDP
AA3
CAS
VCCQL
BCLK
BR
VCCC
AA0
A0
P
NC
H5
H3
H1
PCAP
GNDP1
AA2
XTAL
VCCC
TA
BB
AA1
BG
NC
Figure 3-1 DSP56307 Plastic Ball Grid Array (PBGA), Top View
Not Recommended for New Design
3-2 DSP56307 Technical Data MOTOROLA
Packaging Pin-out and Package Information
Bottom View
14 NC 13 D7 12 D9 11 D11 10 D14 9 D16 8 D19 7 VCCD 6 D23 5 IRQB 4 TDO 3 TMS 2 SC11 1 NC A
NC
D5
D8
D10
D13
D15
D17
D20
D21
IRQD
TRST
TDI
SC12
SRD1
B
D4
D3
D6
VCCD
D12
VCCD
D18
VCCQL
D22
IRQC
IRQA
TCK
STD1
SC02
C
VCCD
D2
D1
GND
GND
GND
GND
GND
GND
GND
GND
DE
SC01
PINIT
D
D0
A16
A17
GND
GND
GND
GND
GND
GND
GND
GND
SRD0
VCCS
STD0
E
A15
A14
VCCQH
GND
GND
GND
GND
GND
GND
GND
GND
SC00
SC10
RXD
F
A12
VCCQL
A13
GND
GND
GND
GND
GND
GND
GND
GND
TXD
SCLK
SCK1
G
A11
A10
VCCA
GND
GND
GND
GND
GND
GND
GND
GND
SCK0
VCCQL
VCCQH H
A9
A7
A8
GND
GND
GND
GND
GND
GND
GND
GND
HDS
HRW
HACK J
A6
A5
VCCA
GND
GND
GND
GND
GND
GND
GND
GND
TIO2
HREQ
VCCS
K
A4
A3
VCCA
GND
GND
GND
GND
GND
GND
GND
GND
TIO0
TIO1
HCS
L
A2
A1
RD
WR
BCLK
CLK OUT
EXTAL
VCCQH
VCCP
PB0
VCCH
HA0
HA2
HA1
M
A0
AA0
VCCC
BR
BCLK
VCCQL
CAS
AA3
GNDP
RESET
H2
H4
H7
H6
N
NC
BG
AA1
BB
TA
VCCC
XTAL
AA2
GNDP1
PCAP
H1
H3
H5
NC
P
Figure 3-2 DSP56307 Plastic Ball Grid Array (PBGA), Bottom View
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 3-3
Packaging Pin-out and Package Information
Table 3-1 DSP56307 PBGA Signal Identification by Pin Number
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Signal Name Not Connected (NC), reserved SC11 or PD1 TMS TDO MODB/IRQB D23 VCCD D19 D16 D14 D11 D9 D7 NC SRD1 or PD4 SC12 or PD2 TDI TRST MODD/IRQD D21 D20 D17 D15 D13 D10 Pin No. B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D8 D5 NC SC02 or PC2 STD1 or PD5 TCK MODA/IRQA MODC/IRQC D22 VCCQL D18 VCCD D12 VCCD D6 D3 D4 PINIT/NMI SC01 or PC1 DE GND GND GND GND GND Signal Name Pin No. D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 GND GND GND D1 D2 VCCD STD0 or PC5 VCCS SRD0 or PC4 GND GND GND GND GND GND GND GND A17 A16 D0 RXD or PE0 SC10 or PD0 SC00 or PC0 GND GND Signal Name
Not Recommended for New Design
3-4 DSP56307 Technical Data MOTOROLA
Packaging Pin-out and Package Information
Table 3-1 DSP56307 PBGA Signal Identification by Pin Number (Continued)
Pin No. F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 GND GND GND GND GND GND VCCQH A14 A15 SCK1 or PD3 SCLK or PE2 TXD or PE1 GND GND GND GND GND GND GND GND A13 VCCQL A12 VCCQH VCCQL Signal Name Pin No. H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 Signal Name SCK0 or PC3 GND GND GND GND GND GND GND GND VCCA A10 A11 HACK/HACK, HRRQ/HRRQ, or PB15 Pin No. J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 A9 VCCS HREQ/HREQ, HTRQ/HTRQ, or PB14 TIO2 GND GND GND GND GND GND GND GND VCCA A5 A6 HCS/HCS, HA10, or PB13 TIO1 TIO0 GND GND GND GND GND GND GND Signal Name
HRW, HRD/HRD, or PB11 K13 HDS/HDS, HWR/HWR, or PB12 GND GND GND GND GND GND GND GND A8 A7 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 3-5
Packaging Pin-out and Package Information
Table 3-1 DSP56307 PBGA Signal Identification by Pin Number (Continued)
Pin No. L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
Note:
Signal Name GND VCCA A3 A4 HA1, HA8, or PB9 HA2, HA9, or PB10 HA0, HAS/HAS, or PB8 VCCH H0, HAD0, or PB0 VCCP VCCQH EXTAL CLKOUT BCLK WR RD
Pin No. M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 A1 A2
Signal Name
Pin No. P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 NC
Signal Name
H5, HAD5, or PB5 H3, HAD3, or PB3 H1, HAD1, or PB1 PCAP GNDP1 AA2/RAS2 XTAL VCCC TA BB AA1/RAS1 BG NC
H6, HAD6, or PB6 H7, HAD7, or PB7 H4, HAD4, or PB4 H2, HAD2, or PB2 RESET GNDP AA3/RAS3 CAS VCCQL BCLK BR VCCC AA0/RAS0 A0
Signal names are based on configured functionality. Most connections supply a single signal. Some connections provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted but act as interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some connections have two or more configurable functions; names assigned to these connections indicate the function for a specific configuration. For example, connection N2 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike the TQFP package, most of the GND pins are connected internally in the center of the connection array and act as heat sink for the chip. Therefore, except for GNDP and GNDP1 that support the PLL, other GND signals do not support individual subsystems in the chip.
Not Recommended for New Design
3-6 DSP56307 Technical Data MOTOROLA
Packaging Pin-out and Package Information
Table 3-2 DSP56307 PBGA Signal Identification by Name
Signal Name A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A2 A3 A4 A5 A6 A7 A8 A9 AA0 AA1 AA2 AA3 BB BCLK BCLK Pin No. N14 M13 H13 H14 G14 G12 F13 F14 E13 E12 M14 L13 L14 K13 K14 J13 J12 J14 N13 P12 P7 N7 P11 M10 N10 Signal Name BG BR CAS CLKOUT D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D3 D4 D5 D6 Pin No. P13 N11 N8 M9 E14 D12 B11 A11 C10 B10 A10 B9 A9 B8 C8 A8 D13 B7 B6 C6 A6 C13 C14 B13 C12 Signal Name D7 D8 D9 DE EXTAL GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin No. A13 B12 A12 D3 M8 D4 D5 D6 D7 D8 D9 D10 D11 E4 E5 E6 E7 E8 E9 E10 E11 F4 F5 F6 F7
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 3-7
Packaging Pin-out and Package Information
Table 3-2 DSP56307 PBGA Signal Identification by Name (Continued)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin No. F8 F9 F10 F11 G4 G5 G6 G7 G8 G9 G10 G11 H4 H5 H6 H7 H8 H9 H10 H11 J4 J5 J6 J7 J8 Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNDP GNDP1 H0 H1 H2 H3 Pin No. J9 J10 J11 K4 K5 K6 K7 K8 K9 K10 K11 L4 L5 L6 L7 L8 L9 L10 L11 N6 P6 M5 P4 N4 P3 Signal Name H4 H5 H6 H7 HA0 HA1 HA10 HA2 HA8 HA9 HACK/HACK HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HAS HCS/HCS HDS/HDS HRD/HRD HREQ/HREQ HRRQ/HRRQ Pin No. N3 P2 N1 N2 M3 M1 L1 M2 M1 M2 J1 M5 P4 N4 P3 N3 P2 N1 N2 M3 L1 J3 J2 K2 J1
Not Recommended for New Design
3-8 DSP56307 Technical Data MOTOROLA
Packaging Pin-out and Package Information
Table 3-2 DSP56307 PBGA Signal Identification by Name (Continued)
Signal Name HRW HTRQ/HTRQ HWR/HWR IRQA IRQB IRQC IRQD MODA MODB MODC MODD NC NC NC NC NC NMI PB0 PB1 PB10 PB11 PB12 PB13 PB14 PB15 Pin No. J2 K2 J3 C4 A5 C5 B5 C4 A5 C5 B5 A1 A14 B14 P1 P14 D1 M5 P4 M2 J2 J3 L1 K2 J1 Signal Name PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PC0 PC1 PC2 PC3 PC4 PC5 PCAP PD0 PD1 PD2 PD3 PD4 PD5 PE0 PE1 PE2 PINIT Pin No. N4 P3 N3 P2 N1 N2 M3 M1 F3 D2 C1 H3 E3 E1 P5 F2 A2 B2 G1 B1 C2 F1 G3 G2 D1 Signal Name RAS0 RAS1 RAS2 RAS3 RD RESET RXD SC00 SC01 SC02 SC10 SC11 SC12 SCK0 SCK1 SCLK SRD0 SRD1 STD0 STD1 TA TCK TDI TDO TIO0 Pin No. N13 P12 P7 N7 M12 N5 F1 F3 D2 C1 F2 A2 B2 H3 G1 G2 E3 B1 E1 C2 P10 C3 B3 A4 L3
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 3-9
Packaging Pin-out and Package Information
Table 3-2 DSP56307 PBGA Signal Identification by Name (Continued)
Signal Name TIO1 TIO2 TMS TRST TXD VCCA VCCA VCCA VCCC Pin No. L2 K3 A3 B4 G3 H12 K12 L12 N12 Signal Name VCCC VCCD VCCD VCCD VCCD VCCH VCCP VCCQH VCCQH Pin No. P9 A7 C9 C11 D14 M4 M6 F12 H1 Signal Name VCCQH VCCQL VCCQL VCCQL VCCQL VCCS VCCS WR XTAL Pin No. M7 C7 G13 H2 N9 E2 K1 M11 P8
Not Recommended for New Design
3-10 DSP56307 Technical Data MOTOROLA
Packaging Pin-out and Package Information
PBGA Package Mechanical Drawing
4X
0.2 B
A
D
C 0.15 C E2 E 0.35 C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE SOLDER BAL DIAMETER MEASURED PARALLEL T DATUM C.
4X R
R1
D2 TOP VIEW D1 e /2
13X
e
P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 1011121314 196X
2X R
R1 A2 A3 A1 A
DIM A A1 A2 A3 b D D1 D2 E E1 E2 e R1
MILLIMETERS MIN MAX 1.91 1.25 0.27 0.47 0.28 0.44 0.70 1.00 0.35 0.65 15.00 BSC 13.00 BSC 12.00 15.00 15.00 BSC 13.00 BSC 12.00 15.00 1.00 BSC -- 2.50
E1 e /2
SIDE VIEW
b 0.3 0.1 CAB C
BOTTOM VIEW
CASE 1128-01 ISSUE B
DATE 11/22/96
Figure 3-3 DSP56307 Mechanical Information, 196-pin PBGA Package
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 3-11
Packaging Ordering Drawings
ORDERING DRAWINGS
Complete mechanical information on DSP56307 packaging is available by facsimile through Motorola's Mfax system. Call the following number to obtain information by facsimile:
(602) 244-6609
The Mfax automated system requests the following information: The receiving facsimile telephone number including area code or country code The callerOs personal identification number (PIN) Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. The type of information requested: Instructions for using the system A literature order form Specific part technical information or data sheets Other information described by the system messages
A total of three documents may be ordered per call. The DSP56307 196-pin PBGA package mechanical drawing is referenced as 1128-01.
Not Recommended for New Design
3-12 DSP56307 Technical Data MOTOROLA
SECTION 4 DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
An estimate of the chip junction temperature, TJ, in C can be obtained from this equation: Equation 1: T J = T A + ( P D x R JA ) Where: TA RJA PD = = = ambient temperature uC package junction-to-ambient thermal resistance uC/W power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance, as in this equation: Equation 2: R JA = R JC + R CA Where: RJA RJC RCA = = = package junction-to-ambient thermal resistance uC/W package junction-to-case thermal resistance uC/W package case-to-ambient thermal resistance uC/W
RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB) or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimates obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 4-1
Design Considerations Thermal Design Considerations
A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed from the value obtained by the equation (TJ - TT)/PD.
As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will yield an estimate of a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when the surface temperature of the package is used. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
Not Recommended for New Design
SECTION 4-2 DSP56307 Technical Data MOTOROLA
Design Considerations Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
Use the following list of recommendations to insure correct DSP operation. Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. Use at least six 0.010.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. Insure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 inch per capacitor lead. Use at least a four-layer PCB with two inner layers for VCC and GND. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended. Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) by CMOS levels except for the three pins with internal pull-up resistors (TRST, TMS, DE). Take special care to minimize noise levels on the VCCP, GNDP, and GNDP1 pins. The following pins must be asserted after power-up: RESET and TRST. If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices.

Not Recommended for New Design
MOTOROLA DSP56307 Technical Data SECTION 4-3
Design Considerations Power Consumption Considerations
RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before deassertion of RESET.
POWER CONSUMPTION CONSIDERATIONS
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by this formula: Equation 3: I = C x V x f Where: C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle Example 1 Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33 MHz), the current consumption is expressed in this equation:
Equation 4:
I = 50 x 10
12
x 3.3 x 33 x 10 = 5.48 mA
6
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditionsNnot necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. Perform the following steps for applications that require very low current consumption: Set the EBD bit when you are not accessing external memory. Minimize external memory accesses, and use internal memory accesses. Minimize the number of pins that are switching. Minimize the capacitive load on the pins. Connect the unused inputs to pull-up or pull-down resistors. Disable unused peripherals. Disable unused pin activity (e.g., CLKOUT, XTAL).
Not Recommended for New Design
SECTION 4-4 DSP56307 Technical Data MOTOROLA
Design Considerations PLL Performance Issues
One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix APPENDIX A Power Consumption Benchmark. Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. Equation 5: I MIPS = I MHz = ( I typF2 I typF1 ) ( F2 F1 ) Where : ItypF2 = current at F2 ItypF1 = current at F1 F2 = high frequency (any specified operating frequency) F1 = low frequency (any specified operating frequency lower than F2) Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application.
PLL PERFORMANCE ISSUES
The following explanations should be considered as general observations on expected PLL behavior. There is no test that replicates these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges.
Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a given capacitive load on CLKOUT over the entire process, temperature, and voltage ranges. As defined in Figure 2-2 on page SECTION 2-7 for input frequencies greater than 15 MHz and the MF 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between -1.4 ns and +3.2 ns.
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data SECTION 4-5
Design Considerations PLL Performance Issues
Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than 2 ns.
Frequency Jitter Performance
The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this jitter is between 0.5% and approximately 2%. For large MF (MF > 500), the frequency jitter is 23%.
Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values.
Not Recommended for New Design
SECTION 4-6 DSP56307 Technical Data MOTOROLA
SECTION 5 ORDERING INFORMATION
Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Ordering Information
Part DSP56307 Supply Voltage 2.5 V core 3.3 V I/O Package Type Plastic Ball Grid Array (PBGA) Pin Count 196 Frequency (MHz) 100 Order Number XC56307GC100C
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data 5-1
Ordering Information
Not Recommended for New Design
SECTION 5-2 DSP56307 Technical Data MOTOROLA
APPENDIX A POWER CONSUMPTION BENCHMARK
The following benchmark program evaluates DSP power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation.
;************************************************************************** ;************************************************************************** ;* * ;* CHECKS Typical Power Consumption * ;* * ;************************************************************************** page nolist I_VEC EQU START EQU INT_PROG INT_XDAT INT_YDAT $000000 $8000 EQU $100 EQU $0 EQU $0 200,55,0,0,0
; ; ; ; ;
Interrupt vectors for program debug only MAIN (external) program starting address INTERNAL program memory starting address INTERNAL X-data memory starting address INTERNAL Y-data memory starting address
INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org ; movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM) ; Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; ; Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; P:START
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-1
Power Consumption Benchmark
move move do move move XLOAD_LOOP ; ; Load the Y-data ; move move do move move YLOAD_LOOP ; jmp PROG_START move move move move ; clr clr move move move move bset ; sbr dor mac mac add mac mac move bra nop nop nop nop PROG_END nop nop
#INT_XDAT,r0 #XDAT_START,r1 #(XDAT_END-XDAT_START),XLOAD_LOOP p:(r1)+,x0 x0,x:(r0)+
#INT_YDAT,r0 #YDAT_START,r1 #(YDAT_END-YDAT_START),YLOAD_LOOP p:(r1)+,x0 x0,y:(r0)+
INT_PROG
#$0,r0 #$0,r4 #$3f,m0 #$3f,m4 a b #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr #60,_end x0,y0,a x1,y1,a a,b x0,y0,a x1,y1,a b1,x:$ff sbr
; ebd
x:(r0)+,x1 x:(r0)+,x0 x:(r0)+,x1
y:(r4)+,y1 y:(r4)+,y0
y:(r4)+,y0
_end
XDAT_START ; org
x:0
Not Recommended for New Design
A-2 DSP56307 Technical Data MOTOROLA
Power Consumption Benchmark
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
$262EB9 $86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E $CFFB2F $40753C $8262C5
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-3
Power Consumption Benchmark
dc dc dc dc dc dc dc dc dc dc dc XDAT_END YDAT_START ; org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
$CA641A $EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127 $482FD4 $7257D $E53C72 $1A8C3 $E27540
y:0 $5B6DA $C3F70B $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48 $EF7AE1 $6E3006 $62F6C7
Not Recommended for New Design
A-4 DSP56307 Technical Data MOTOROLA
Power Consumption Benchmark
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc YDAT_END
$6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245
;************************************************************************** ; ; EQUATES for DSP56307 I/O registers and ports ; ; Last update: June 11 1995 ; ;************************************************************************** page opt ioequ ident 1,0 132,55,0,0,0 mex
;-----------------------------------------------------------------------; ; EQUATES for I/O Port Programming ; ;-----------------------------------------------------------------------; Register Addresses ; Host port GPIO data Register ; Host port GPIO direction Register ; Port C Control Register ; Port C Direction Register
M_HDR EQU $FFFFC9 M_HDDR EQU $FFFFC8 M_PCRC EQU $FFFFBF M_PRRC EQU $FFFFBE
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-5
Power Consumption Benchmark
M_PDRC M_PCRD M_PRRD M_PDRD M_PCRE M_PRRE M_PDRE M_OGDB
EQU EQU EQU EQU EQU EQU EQU EQU
$FFFFBD $FFFFAF $FFFFAE $FFFFAD $FFFF9F $FFFF9E $FFFF9D $FFFFFC
; ; ; ; ; ; ; ;
Port Port Port Port Port Port Port OnCE
C GPIO Data Register D Control register D Direction Data Register D GPIO Data Register E Control register E Direction Register E Data Register GDB Register
;-----------------------------------------------------------------------; ; EQUATES for Host Interface ; ;-----------------------------------------------------------------------; Register Addresses ; ; ; ; ; ; Host Host Host Host Host Host Control Register Status Rgister Polarity Control Register Base Address Register Receive Register Transmit Register
M_HCR EQU $FFFFC2 M_HSR EQU $FFFFC3 M_HPCR EQU $FFFFC4 M_HBAR EQU $FFFFC5 M_HRX EQU $FFFFC6 M_HTX EQU $FFFFC7 ; HCR bits definition M_HRIE EQU $0 M_HTIE EQU $1 M_HCIE EQU $2 M_HF2 EQU $3 M_HF3 EQU $4 ; HSR bits definition M_HRDF EQU $0 M_HTDE EQU $1 M_HCP EQU $2 M_HF0 EQU $3 M_HF1 EQU $4
; ; ; ; ;
Host Host Host Host Host
Receive interrupts Enable Transmit Interrupt Enable Command Interrupt Enable Flag 2 Flag 3
; ; ; ; ;
Host Host Host Host Host
Receive Data Full Receive Data Emptiy Command Pending Flag 0 Flag 1
; HPCR bits definition M_HGEN EQU $0 M_HA8EN EQU $1 M_HA9EN EQU $2 M_HCSEN EQU $3 M_HREN EQU $4 M_HAEN EQU $5 M_HEN EQU $6 M_HOD EQU $8 M_HDSP EQU $9 M_HASP EQU $A M_HMUX EQU $B M_HD_HS EQU $C
; ; ; ; ; ; ; ; ; ; ; ;
Host Host Host Host Host Host Host Host Host Host Host Host
Port GPIO Enable Address 8 Enable Address 9 Enable Chip Select Enable Request Enable Acknowledge Enable Enable Request Open Drain mode Data Strobe Polarity Address Strobe Polarity Multiplexed bus select Double/Single Strobe select
Not Recommended for New Design
A-6 DSP56307 Technical Data MOTOROLA
Power Consumption Benchmark
M_HCSP EQU $D M_HRP EQU $E M_HAP EQU $F
; Host Chip Select Polarity ; Host Request PolarityPolarity ; Host Acknowledge Polarity
;-----------------------------------------------------------------------; ; EQUATES for Serial Communications Interface (SCI) ; ;-----------------------------------------------------------------------; Register Addresses ; ; ; ; ; ; ; ; ; ; SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI Transmit Data Register (high) Transmit Data Register (middle) Transmit Data Register (low) Receive Data Register (high) Receive Data Register (middle) Receive Data Register (low) Transmit Address Register Control Register Status Register Clock Control Register
M_STXH EQU $FFFF97 M_STXM EQU $FFFF96 M_STXL EQU $FFFF95 M_SRXH EQU $FFFF9A M_SRXM EQU $FFFF99 M_SRXL EQU $FFFF98 M_STXA EQU $FFFF94 M_SCR EQU $FFFF9C M_SSR EQU $FFFF93 M_SCCR EQU $FFFF9B ;
SCI Control Register Bit Flags ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Word Select Mask (WDS0-WDS3) Word Select 0 Word Select 1 Word Select 2 SCI Shift Direction Send Break Wakeup Mode Select Receiver Wakeup Enable Wired-OR Mode Select SCI Receiver Enable SCI Transmitter Enable Idle Line Interrupt Enable SCI Receive Interrupt Enable SCI Transmit Interrupt Enable Timer Interrupt Enable Timer Interrupt Rate SCI Clock Polarity SCI Error Interrupt Enable (REIE)
M_WDS EQU $7 M_WDS0 EQU 0 M_WDS1 EQU 1 M_WDS2 EQU 2 M_SSFTD EQU 3 M_SBK EQU 4 M_WAKE EQU 5 M_RWU EQU 6 M_WOMS EQU 7 M_SCRE EQU 8 M_SCTE EQU 9 M_ILIE EQU 10 M_SCRIE EQU 11 M_SCTIE EQU 12 M_TMIE EQU 13 M_TIR EQU 14 M_SCKP EQU 15 M_REIE EQU 16 ;
SCI Status Register Bit Flags 0 1 2 3 ; ; ; ; ; ; Transmitter Empty Transmit Data Register Empty Receive Data Register Full Idle Line Flag Overrun Error Flag Parity Error
M_TRNE EQU M_TDRE EQU M_RDRF EQU M_IDLE EQU M_OR EQU 4 M_PE EQU 5
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-7
Power Consumption Benchmark
M_FE EQU 6 M_R8 EQU 7 ; r
; Framing Error Flag ; Received Bit 8 (R8) Address
SCI Clock Control Registe
M_CD EQU $FFF M_COD EQU 12 M_SCP EQU 13 M_RCM EQU 14 M_TCM EQU 15
; ; ; ; ;
Clock Divider Mask (CD0-CD11) Clock Out Divider Clock Prescaler Receive Clock Mode Source Bit Transmit Clock Source Bit
;-----------------------------------------------------------------------; ; EQUATES for Synchronous Serial Interface (SSI) ; ;-----------------------------------------------------------------------; ; Register Addresses Of SSI0 M_TX00 EQU $FFFFBC ; SSI0 Transmit Data Register 0 M_TX01 EQU $FFFFBB ; SSIO Transmit Data Register 1 M_TX02 EQU $FFFFBA ; SSIO Transmit Data Register 2 M_TSR0 EQU $FFFFB9 ; SSI0 Time Slot Register M_RX0 EQU $FFFFB8 ; SSI0 Receive Data Register M_SSISR0 EQU $FFFFB7 ; SSI0 Status Register M_CRB0 EQU $FFFFB6 ; SSI0 Control Register B M_CRA0 EQU $FFFFB5 ; SSI0 Control Register A M_TSMA0 EQU $FFFFB4 ; SSI0 Transmit Slot Mask Register A M_TSMB0 EQU $FFFFB3 ; SSI0 Transmit Slot Mask Register B M_RSMA0 EQU $FFFFB2 ; SSI0 Receive Slot Mask Register A M_RSMB0 EQU $FFFFB1 ; SSI0 Receive Slot Mask Register B ; Register Addresses Of SSI1 M_TX10 EQU $FFFFAC ; SSI1 Transmit Data Register 0 M_TX11 EQU $FFFFAB ; SSI1 Transmit Data Register 1 M_TX12 EQU $FFFFAA ; SSI1 Transmit Data Register 2 M_TSR1 EQU $FFFFA9 ; SSI1 Time Slot Register M_RX1 EQU $FFFFA8 ; SSI1 Receive Data Register M_SSISR1 EQU $FFFFA7 ; SSI1 Status Register M_CRB1 EQU $FFFFA6 ; SSI1 Control Register B M_CRA1 EQU $FFFFA5 ; SSI1 Control Register A M_TSMA1 EQU $FFFFA4 ; SSI1 Transmit Slot Mask Register A M_TSMB1 EQU $FFFFA3 ; SSI1 Transmit Slot Mask Register B M_RSMA1 EQU $FFFFA2 ; SSI1 Receive Slot Mask Register A M_RSMB1 EQU $FFFFA1 ; SSI1 Receive Slot Mask Register B ; SSI Control Register A Bit Flags ; ; ; ; Prescale Modulus Select Mask (PM0-PM7) Prescaler Range Frame Rate Divider Control Mask (DC0-DC7) Alignment Control (ALC)
M_PM EQU $FF M_PSR EQU 11 M_DC EQU $1F000 M_ALC EQU 18
Not Recommended for New Design
A-8 DSP56307 Technical Data MOTOROLA
Power Consumption Benchmark
M_WL EQU $380000 M_SSC1 EQU 22 ;
; Word Length Control Mask (WL0-WL7) ; Select SC1 as TR #0 drive enable (SSC1)
SSI Control Register B Bit Flags ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Serial Output Flag Mask Serial Output Flag 0 Serial Output Flag 1 Serial Control Direction Mask Serial Control 0 Direction Serial Control 1 Direction Serial Control 2 Direction Clock Source Direction Shift Direction Frame Sync Length Mask (FSL0-FSL1) Frame Sync Length 0 Frame Sync Length 1 Frame Sync Relative Timing Frame Sync Polarity Clock Polarity Sync/Async Control SSI Mode Select SSI Transmit enable Mask SSI Transmit #2 Enable SSI Transmit #1 Enable SSI Transmit #0 Enable SSI Receive Enable SSI Transmit Interrupt Enable SSI Receive Interrupt Enable SSI Transmit Last Slot Interrupt Enable SSI Receive Last Slot Interrupt Enable SSI Transmit Error Interrupt Enable SI Receive Error Interrupt Enable
M_OF EQU $3 M_OF0 EQU 0 M_OF1 EQU 1 M_SCD EQU $1C M_SCD0 EQU 2 M_SCD1 EQU 3 M_SCD2 EQU 4 M_SCKD EQU 5 M_SHFD EQU 6 M_FSL EQU $180 M_FSL0 EQU 7 M_FSL1 EQU 8 M_FSR EQU 9 M_FSP EQU 10 M_CKP EQU 11 M_SYN EQU 12 M_MOD EQU 13 M_SSTE EQU $1C000 M_SSTE2 EQU 14 M_SSTE1 EQU 15 M_SSTE0 EQU 16 M_SSRE EQU 17 M_SSTIE EQU 18 M_SSRIE EQU 19 M_STLIE EQU 20 M_SRLIE EQU 21 M_STEIE EQU 22 M_SREIE EQU 23 ;
SSI Status Register Bit Flags ; ; ; ; ; ; ; ; ; Serial Input Flag Mask Serial Input Flag 0 Serial Input Flag 1 Transmit Frame Sync Flag Receive Frame Sync Flag Transmitter Underrun Error FLag Receiver Overrun Error Flag Transmit Data Register Empty Receive Data Register Full
M_IF EQU $3 M_IF0 EQU 0 M_IF1 EQU 1 M_TFS EQU 2 M_RFS EQU 3 M_TUE EQU 4 M_ROE EQU 5 M_TDE EQU 6 M_RDF EQU 7 ;
SSI Transmit Slot Mask Register A ; SSI Transmit Slot Bits Mask A (TS0-TS15)
M_SSTSA EQU $FFFF ;
SSI Transmit Slot Mask Register B ; SSI Transmit Slot Bits Mask B (TS16-TS31)
M_SSTSB EQU $FFFF
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-9
Power Consumption Benchmark
;
SSI Receive Slot Mask Register A ; SSI Receive Slot Bits Mask A (RS0-RS15)
M_SSRSA EQU $FFFF ;
SSI Receive Slot Mask Register B ; SSI Receive Slot Bits Mask B (RS16-RS31)
M_SSRSB EQU $FFFF
;-----------------------------------------------------------------------; ; EQUATES for Exception Processing ; ;------------------------------------------------------------------------
;
Register Addresses ; Interrupt Priority Register Core ; Interrupt Priority Register Peripheral
M_IPRC EQU $FFFFFF M_IPRP EQU $FFFFFE ;
Interrupt Priority Register Core (IPRC) ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; IRQA IRQA IRQA IRQA IRQB IRQB IRQB IRQB IRQC IRQC IRQC IRQC IRQD IRQD IRQD IRQD DMA0 DMA0 DMA0 DMA1 DMA1 DMA1 DMA2 DMA2 DMA2 DMA3 DMA3 DMA3 Mode Mask Mode Interrupt Priority Level (low) Mode Interrupt Priority Level (high) Mode Trigger Mode Mode Mask Mode Interrupt Priority Level (low) Mode Interrupt Priority Level (high) Mode Trigger Mode Mode Mask Mode Interrupt Priority Level (low) Mode Interrupt Priority Level (high) Mode Trigger Mode Mode Mask Mode Interrupt Priority Level (low) Mode Interrupt Priority Level (high) Mode Trigger Mode Interrupt priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) Interrupt Priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) Interrupt priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) Interrupt Priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high)
M_IAL EQU $7 M_IAL0 EQU 0 M_IAL1 EQU 1 M_IAL2 EQU 2 M_IBL EQU $38 M_IBL0 EQU 3 M_IBL1 EQU 4 M_IBL2 EQU 5 M_ICL EQU $1C0 M_ICL0 EQU 6 M_ICL1 EQU 7 M_ICL2 EQU 8 M_IDL EQU $E00 M_IDL0 EQU 9 M_IDL1 EQU 10 M_IDL2 EQU 11 M_D0L EQU $3000 M_D0L0 EQU 12 M_D0L1 EQU 13 M_D1L EQU $C000 M_D1L0 EQU 14 M_D1L1 EQU 15 M_D2L EQU $30000 M_D2L0 EQU 16 M_D2L1 EQU 17 M_D3L EQU $C0000 M_D3L0 EQU 18 M_D3L1 EQU 19
Not Recommended for New Design
A-10 DSP56307 Technical Data MOTOROLA
Power Consumption Benchmark
M_D4L EQU $300000 M_D4L0 EQU 20 M_D4L1 EQU 21 M_D5L EQU $C00000 M_D5L0 EQU 22 M_D5L1 EQU 23
; ; ; ; ; ;
DMA4 DMA4 DMA4 DMA5 DMA5 DMA5
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
priority Priority Priority priority Priority Priority
Level Level Level Level Level Level
Mask (low) (high) Mask (low) (high)
;
Interrupt Priority Register Peripheral (IPRP) ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Host Interrupt Priority Level Mask Host Interrupt Priority Level (low) Host Interrupt Priority Level (high) SSI0 Interrupt Priority Level Mask SSI0 Interrupt Priority Level (low) SSI0 Interrupt Priority Level (high) SSI1 Interrupt Priority Level Mask SSI1 Interrupt Priority Level (low) SSI1 Interrupt Priority Level (high) SCI Interrupt Priority Level Mask SCI Interrupt Priority Level (low) SCI Interrupt Priority Level (high) TIMER Interrupt Priority Level Mask TIMER Interrupt Priority Level (low) TIMER Interrupt Priority Level (high)
M_HPL EQU $3 M_HPL0 EQU 0 M_HPL1 EQU 1 M_S0L EQU $C M_S0L0 EQU 2 M_S0L1 EQU 3 M_S1L EQU $30 M_S1L0 EQU 4 M_S1L1 EQU 5 M_SCL EQU $C0 M_SCL0 EQU 6 M_SCL1 EQU 7 M_T0L EQU $300 M_T0L0 EQU 8 M_T0L1 EQU 9
;-----------------------------------------------------------------------; ; EQUATES for TIMER ; ;-----------------------------------------------------------------------; Register Addresses Of TIMER0 $FFFF8F $FFFF8E $FFFF8D $FFFF8C ; ; ; ; Timer 0 Control/Status Register TIMER0 Load Reg TIMER0 Compare Register TIMER0 Count Register
M_TCSR0 EQU M_TLR0 EQU M_TCPR0 EQU M_TCR0 EQU ;
Register Addresses Of TIMER1 $FFFF8B $FFFF8A $FFFF89 $FFFF88 ; ; ; ; TIMER1 TIMER1 TIMER1 TIMER1 Control/Status Register Load Reg Compare Register Count Register
M_TCSR1 EQU M_TLR1 EQU M_TCPR1 EQU M_TCR1 EQU
;
Register Addresses Of TIMER2
M_TCSR2 EQU $FFFF87 ; TIMER2 Control/Status Register M_TLR2 EQU $FFFF86 ; TIMER2 Load Reg M_TCPR2 EQU $FFFF85 ; TIMER2 Compare Register
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-11
Power Consumption Benchmark
M_TCR2 EQU M_TPLR EQU M_TPCR EQU
$FFFF84 $FFFF83 $FFFF82
; TIMER2 Count Register ; TIMER Prescaler Load Register ; TIMER Prescalar Count Register
;
Timer Control/Status Register Bit Flags ; ; ; ; ; ; ; ; ; ; ; ; Timer Enable Timer Overflow Interrupt Enable Timer Compare Interrupt Enable Timer Control Mask (TC0-TC3) Inverter Bit Timer Restart Mode Direction Bit Data Input Data Output Prescaled Clock Enable Timer Overflow Flag Timer Compare Flag
M_TE EQU 0 M_TOIE EQU 1 M_TCIE EQU 2 M_TC EQU $F0 M_INV EQU 8 M_TRM EQU 9 M_DIR EQU 11 M_DI EQU 12 M_DO EQU 13 M_PCE EQU 15 M_TOF EQU 20 M_TCF EQU 21 ;
Timer Prescaler Register Bit Flags ; Prescaler Source Mask
M_PS EQU $600000 M_PS0 EQU 21 M_PS1 EQU 22 ; M_TC0 M_TC1 M_TC2 M_TC3
EQU EQU EQU EQU
Timer Control Bits 4 ; Timer Control 5 ; Timer Control 6 ; Timer Control 7 ; Timer Control
0 1 2 3
;-----------------------------------------------------------------------; ; EQUATES for Direct Memory Access (DMA) ; ;-----------------------------------------------------------------------; M_DSTR M_DOR0 M_DOR1 M_DOR2 M_DOR3 Register Addresses Of DMA EQU FFFFF4 ; DMA Status Register EQU $FFFFF3 ; DMA Offset Register 0 EQU $FFFFF2 ; DMA Offset Register 1 EQU $FFFFF1 ; DMA Offset Register 2 EQU $FFFFF0 ; DMA Offset Register 3
; M_DSR0 M_DDR0 M_DCO0 M_DCR0
Register Addresses Of DMA0 EQU EQU EQU EQU $FFFFEF $FFFFEE $FFFFED $FFFFEC ; ; ; ; DMA0 DMA0 DMA0 DMA0 Source Address Register Destination Address Register Counter Control Register
Not Recommended for New Design
A-12 DSP56307 Technical Data MOTOROLA
Power Consumption Benchmark
; M_DSR1 M_DDR1 M_DCO1 M_DCR1 ; M_DSR2 M_DDR2 M_DCO2 M_DCR2 ; M_DSR3 M_DDR3 M_DCO3 M_DCR3 ;
Register Addresses Of DMA1 EQU EQU EQU EQU $FFFFEB $FFFFEA $FFFFE9 $FFFFE8 ; ; ; ; DMA1 DMA1 DMA1 DMA1 Source Address Register Destination Address Register Counter Control Register
Register Addresses Of DMA2 EQU EQU EQU EQU $FFFFE7 $FFFFE6 $FFFFE5 $FFFFE4 ; ; ; ; DMA2 DMA2 DMA2 DMA2 Source Address Register Destination Address Register Counter Control Register
Register Addresses Of DMA4 EQU EQU EQU EQU $FFFFE3 $FFFFE2 $FFFFE1 $FFFFE0 ; ; ; ; DMA3 DMA3 DMA3 DMA3 Source Address Register Destination Address Register Counter Control Register
Register Addresses Of DMA4
M_DSR4 M_DDR4 M_DCO4 M_DCR4 ; M_DSR5 M_DDR5 M_DCO5 M_DCR5 ;
EQU EQU EQU EQU
$FFFFDF $FFFFDE $FFFFDD $FFFFDC
; ; ; ;
DMA4 DMA4 DMA4 DMA4
Source Address Register Destination Address Register Counter Control Register
Register Addresses Of DMA5 EQU EQU EQU EQU $FFFFDB $FFFFDA $FFFFD9 $FFFFD8 ; ; ; ; DMA5 DMA5 DMA5 DMA5 Source Address Register Destination Address Register Counter Control Register
DMA Control Register ; ; ; ; ; ; ; ; ; ; ; ; ; ; DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA Source Space Mask (DSS0-Dss1) Source Memory space 0 Source Memory space 1 Destination Space Mask (DDS-DDS1) Destination Memory Space 0 Destination Memory Space 1 Address Mode Mask (DAM5-DAM0) Address Mode 0 Address Mode 1 Address Mode 2 Address Mode 3 Address Mode 4 Address Mode 5 Three Dimensional Mode
M_DSS EQU $3 M_DSS0 EQU 0 M_DSS1 EQU 1 M_DDS EQU $C M_DDS0 EQU 2 M_DDS1 EQU 3 M_DAM EQU $3f0 M_DAM0 EQU 4 M_DAM1 EQU 5 M_DAM2 EQU 6 M_DAM3 EQU 7 M_DAM4 EQU 8 M_DAM5 EQU 9 M_D3D EQU 10
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-13
Power Consumption Benchmark
M_DRS EQU $F800 M_DCON EQU 16 M_DPR EQU $60000 M_DPR0 EQU 17 M_DPR1 EQU 18 M_DTM EQU $380000 M_DTM0 EQU 19 M_DTM1 EQU 20 M_DTM2 EQU 21 M_DIE EQU 22 M_DE EQU 23 ;
; ; ; ; ; ; ; ; ; ; ;
DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA
Request Source Mask (DRS0-DRS4) Continuous Mode Channel Priority Channel Priority Level (low) Channel Priority Level (high) Transfer Mode Mask (DTM2-DTM0) Transfer Mode 0 Transfer Mode 1 Transfer Mode 2 Interrupt Enable bit Channel Enable bit
DMA Status Register ; ; ; ; ; ; ; ; ; ; ; ; Channel Transfer Done Status MASK (DTD0-DTD5) DMA Channel Transfer Done Status 0 DMA Channel Transfer Done Status 1 DMA Channel Transfer Done Status 2 DMA Channel Transfer Done Status 3 DMA Channel Transfer Done Status 4 DMA Channel Transfer Done Status 5 DMA Active State DMA Active Channel Mask (DCH0-DCH2) DMA Active Channel 0 DMA Active Channel 1 DMA Active Channel 2
M_DTD EQU $3F M_DTD0 EQU 0 M_DTD1 EQU 1 M_DTD2 EQU 2 M_DTD3 EQU 3 M_DTD4 EQU 4 M_DTD5 EQU 5 M_DACT EQU 8 M_DCH EQU $E00 M_DCH0 EQU 9 M_DCH1 EQU 10 M_DCH2 EQU 11
;-----------------------------------------------------------------------; ; EQUATES for Enhanced Filter Co-Processop (EFCOP) ; ;-----------------------------------------------------------------------M_FDIR M_FDOR M_FKIR M_FCNT M_FCSR M_FACR M_FDBA M_FCBA M_FDCH EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFB0 $FFFFB1 $FFFFB2 $FFFFB3 $FFFFB4 $FFFFB5 $FFFFB6 $FFFFB7 $FFFFB8 ; ; ; ; ; ; ; ; ; EFCOP EFCOP EFCOP EFCOP EFCOP EFCOP EFCOP EFCOP EFCOP Data Input Register Data Output Register K-Constant Register Filter Counter Control Status Register ALU Control Register Data Base Address Coefficient Base Address Decimation/Channel Register
;-----------------------------------------------------------------------; ; EQUATES for Phase Locked Loop (PLL) ; ;-----------------------------------------------------------------------; Register Addresses Of PLL
Not Recommended for New Design
A-14 DSP56307 Technical Data MOTOROLA
Power Consumption Benchmark
M_PCTL EQU $FFFFFD ;
; PLL Control Register
PLL Control Register : ; ; ; ; ; ; ; Multiplication Factor Bits Mask (MF0-MF11) Division Factor Bits Mask (DF0-DF2) XTAL Range select bit XTAL Disable Bit STOP Processing State Bit PLL Enable Bit PLL Clock Output Disable Bit PreDivider Factor Bits Mask (PD0-PD3)
M_MF EQU $FFF M_DF EQU $7000 M_XTLR EQU 15 M_XTLD EQU 16 M_PSTP EQU 17 M_PEN EQU 18 M_PCOD EQU 19 M_PD EQU $F00000
;-----------------------------------------------------------------------; ; EQUATES for BIU ; ;-----------------------------------------------------------------------; Register Addresses Of BIU
M_BCR EQU $FFFFFB M_DCR EQU $FFFFFA M_AAR0 EQU $FFFFF9 M_AAR1 EQU $FFFFF8 M_AAR2 EQU $FFFFF7 M_AAR3 EQU $FFFFF6 M_IDR EQU $FFFFF5 ;
; ; ; ; ; ; ;
Bus Control Register DRAM Control Register Address Attribute Register Address Attribute Register Address Attribute Register Address Attribute Register ID Register
0 1 2 3
Bus Control Register ; ; ; ; ; ; ; ; Area 0 Wait Control Mask (BA0W0-BA0W4) Area 1 Wait Control Mask (BA1W0-BA14) Area 2 Wait Control Mask (BA2W0-BA2W2) Area 3 Wait Control Mask (BA3W0-BA3W3) Default Area Wait Control Mask (BDFW0-BDFW4) Bus State Bus Lock Hold Bus Request Hold
M_BA0W EQU $1F M_BA1W EQU $3E0 M_BA2W EQU $1C00 M_BA3W EQU $E000 M_BDFW EQU $1F0000 M_BBS EQU 21 M_BLH EQU 22 M_BRH EQU 23 ;
DRAM Control Register ; ; ; ; ; ; ; ; In Page Wait States Bits Mask (BCW0-BCW1) Out Of Page Wait States Bits Mask (BRW0-BRW1) DRAM Page Size Bits Mask (BPS0-BPS1) Page Logic Enable Mastership Enable Refresh Enable Software Triggered Refresh Refresh Rate Bits Mask (BRF0-BRF7)
M_BCW EQU $3 M_BRW EQU $C M_BPS EQU $300 M_BPLE EQU 11 M_BME EQU 12 M_BRE EQU 13 M_BSTR EQU 14 M_BRF EQU $7F8000
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-15
Power Consumption Benchmark
M_BRP EQU 23 ;
; Refresh prescaler
Address Attribute Registers ; ; ; ; ; ; ; ; ; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1) Address Attribute Pin Polarity Program Space Enable X Data Space Enable Y Data Space Enable Address Muxing Packing Enable Number of Address Bits to Compare Mask (BNC0-BNC3) Address to Compare Bits Mask (BAC0-BAC11)
M_BAT EQU $3 M_BAAP EQU 2 M_BPEN EQU 3 M_BXEN EQU 4 M_BYEN EQU 5 M_BAM EQU 6 M_BPAC EQU 7 M_BNC EQU $F00 M_BAC EQU $FFF000
;
control and status bits in SR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; mask for CORE-DMA priority bits in SR Carry Overflow Zero Negative Unnormalized Extension Limit Scaling Bit Interupt Mask Bit 0 Interupt Mask Bit 1 Scaling Mode Bit 0 Scaling Mode Bit 1 Sixteen_Bit Compatibility Double Precision Multiply DO-Loop Flag DO-Forever Flag Sixteen-Bit Arithmetic Instruction Cache Enable Arithmetic Saturation Rounding Mode bit 0 of priority bits in SR bit 1 of priority bits in SR
M_CP EQU $c00000 M_CA EQU 0 M_V EQU 1 M_Z EQU 2 M_N EQU 3 M_U EQU 4 M_E EQU 5 M_L EQU 6 M_S EQU 7 M_I0 EQU 8 M_I1 EQU 9 M_S0 EQU 10 M_S1 EQU 11 M_SC EQU 13 M_DM EQU 14 M_LF EQU 15 M_FV EQU 16 M_SA EQU 17 M_CE EQU 19 M_SM EQU 20 M_RM EQU 21 M_CP0 EQU 22 M_CP1 EQU 23
; control and status bits in OMR M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMR M_MA equ0 ; Operating Mode A M_MB equ1 ; Operating Mode B M_MC equ2 ; Operating Mode C M_MD equ3 ; Operating Mode D M_EBD EQU 4 ; External Bus Disable bit in OMR M_SD EQU 6 ; Stop Delay M_MS EQU 7 ; Memory Switch bit in OMR M_CDP0 EQU 8 ; bit 0 of priority bits in OMR M_CDP1 EQU 9 ; bit 1 of priority bits in OMR M_BEN EQU 10 ; Burst Enable
Not Recommended for New Design
A-16 DSP56307 Technical Data MOTOROLA
Power Consumption Benchmark
M_TAS M_BRT M_ATE M_XYS M_EUN M_EOV M_WRP M_SEN
EQU 11 EQU 12 EQU 15 EQU 16 EQU 17 EQU 18 EQU 19 EQU 20
; ; ; ; ; ; ; ;
TA Synchronize Select Bus Release Timing Address Tracing Enable bit in OMR. Stack Extension space select bit in OMR. Extensed stack UNderflow flag in OMR. Extended stack OVerflow flag in OMR. Extended WRaP flag in OMR. Stack Extension Enable bit in OMR.
;************************************************************************* ; ; EQUATES for DSP56307 interrupts ; ; Last update: June 11 1995 ; ;************************************************************************* page opt intequ ident 1,0 132,55,0,0,0 mex
if @DEF(I_VEC) ;leave user definition as is. else I_VEC EQU $0 endif ;-----------------------------------------------------------------------; Non-Maskable interrupts ;-----------------------------------------------------------------------I_RESET EQU I_VEC+$00 ; Hardware RESET I_STACK EQU I_VEC+$02 ; Stack Error I_ILL EQU I_VEC+$04 ; Illegal Instruction I_DBG EQU I_VEC+$06 ; Debug Request I_TRAP EQU I_VEC+$08 ; Trap I_NMI EQU I_VEC+$0A ; Non Maskable Interrupt ;-----------------------------------------------------------------------; Interrupt Request Pins ;-----------------------------------------------------------------------I_IRQA EQU I_VEC+$10 ; IRQA I_IRQB EQU I_VEC+$12 ; IRQB I_IRQC EQU I_VEC+$14 ; IRQC I_IRQD EQU I_VEC+$16 ; IRQD ;------------------------------------------------------------------------
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-17
Power Consumption Benchmark
; DMA Interrupts ;-----------------------------------------------------------------------I_DMA0 EQU I_VEC+$18 ; DMA Channel 0 I_DMA1 EQU I_VEC+$1A ; DMA Channel 1 I_DMA2 EQU I_VEC+$1C ; DMA Channel 2 I_DMA3 EQU I_VEC+$1E ; DMA Channel 3 I_DMA4 EQU I_VEC+$20 ; DMA Channel 4 I_DMA5 EQU I_VEC+$22 ; DMA Channel 5 ;-----------------------------------------------------------------------; Timer Interrupts ;-----------------------------------------------------------------------I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare I_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflow I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare I_TIM2OF EQU I_VEC+$2E ; TIMER 2 overflow ;-----------------------------------------------------------------------; ESSI Interrupts ;-----------------------------------------------------------------------I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data w/ exception Status I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data w/ exception Status I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data w/ exception Status I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data w/ exception Status I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot ;-----------------------------------------------------------------------; SCI Interrupts ;-----------------------------------------------------------------------I_SCIRD EQU I_VEC+$50 ; SCI Receive Data I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status I_SCITD EQU I_VEC+$54 ; SCI Transmit Data I_SCIIL EQU I_VEC+$56 ; SCI Idle Line I_SCITM EQU I_VEC+$58 ; SCI Timer ;-----------------------------------------------------------------------; HOST Interrupts ;-----------------------------------------------------------------------I_HRDF EQU I_VEC+$60 ; Host Receive Data Full I_HTDE EQU I_VEC+$62 ; Host Transmit Data Empty I_HC EQU I_VEC+$64 ; Default Host Command ;----------------------------------------------------------------------; EFCOP Filter Interrupts ;-----------------------------------------------------------------------
Not Recommended for New Design
A-18 DSP56307 Technical Data MOTOROLA
Power Consumption Benchmark
I_FDIIE I_FDOIE
EQU EQU
I_VEC+$68 I_VEC+$6A
; EFilter input buffer empty ; EFilter output buffer full
;-----------------------------------------------------------------------; INTERRUPT ENDING ADDRESS ;-----------------------------------------------------------------------I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data A-19
Power Consumption Benchmark
NOTES:
Not Recommended for New Design
A-20 DSP56307 Technical Data MOTOROLA
INDEX
A
ABE bit in OMR 2-50 AC electrical characteristics 2-4 Access 2-47 address bus 1-1 Address Trace mode 2-50 address tracing mode iii address, electronic mail ii ALU iii applications v arbitration bus timings 2-50 Arithmetic Logic Unit iii Asynchronous Bus Arbitration mode 2-50 ATE bit in OMR 2-50 external indication 1-30 Debug support iii design considerations electrical 4-3 PLL 4-5, 4-6 power consumption 4-4 thermal 4-1 Direct Memory Access iii DMA iii document conventions ii documentation list vi Double Data Strobe 1-2 DRAM controller iv out of page
B
benchmark test algorithm 3 bootstrap programs see appendix of UserOs Manual bootstrap ROM iii boundary scan (JTAG) timing diagram 2-72 bus acquisition timings 2-51 address 1-2 control 1-1 data 1-2 external address 1-6 external data 1-6 multiplexed 1-2 non-multiplexed 1-2 release timings 2-52, 2-53
read access 2-44 Wait states selection guide 2-32 write access 2-45
out of page and refresh timings
11 Wait states 2-38 15 Wait states 2-41 4 Wait states 2-32 8 Wait states 2-35
Page mode
read accesses 2-31 Wait states selection guide 2-21 write accesses 2-30
Page mode timings
C
clock 1-1, 1-5 external 2-4 internal 2-4 operation 2-7 contents ii crystal oscillator circuits 2-6
1 Wait state 2-22 2 Wait states 2-24 3 Wait states 2-26 4 Wait states 2-28 refresh access 2-46 DS 1-2
DSP56300 core features iii Family Manual vi DSP56307 block diagram 1 description 1 features iii specifications 2-1 Technical Data vi UserOs Manual vi
D
Data Arithmetic Logic Unit iii data bus 1-1 data memory expansion iv DC electrical characteristics 2-3 DE signal 1-30 Debug Event signal (DE signal) 1-30 Debug mode entering 1-30
E
EFCOP iii interrupts 20
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data I-1
F
electrical design considerations 4-3 Enhanced Synchronous Serial Interface 1-1 Enhanced Synchronous Serial Interface (ESSI)
Host Interface timing 2-54 Host Port Control Register (HPCR)
1-14, 1-15, 1-
1-
16, 1-17, 1-18, 1-19
Host Request Double 1-2 Single 1-2 HPCR register 1-14,
20, 1-23
Enhanced Synchronous Serial Interfaces v equates see appendix of UserOs Manual ESSI v, 1-1, 1-2, 1-20, 1-23 receiver timing 2-67 timings 2-63 transmitter timing 2-66 external address bus 1-6 external bus control 1-6, 1-8, 1-9 external bus synchronous timings 2-47 external clock operation 2-4 external data bus 1-6 external interrupt timing (negative edge-triggered)
1-15, 1-16, 1-17, 1-18, 1-
19 HR 1-2 I
information sources vi instruction cache iii internal clocks 2-4 internet address ii interrupt and mode control 1-1, 1-11 interrupt control 1-11 interrupt timing 2-10 external level-sensitive fast 2-15 external negative edge-triggered 2-15 synchronous from Wait state 2-16 interrupts EFCOP 20 see appendix of UserOs Manual
2-15
external level-sensitive fast interrupt timing 2-15 external memory access (DMA Source) timing 2-
17
external memory expansion port 1-6 External Memory Interface 2-18 External Memory Interface (Port A) 2-18
F
Filtering Coprocessor iii functional groups 1-2 functional signal groups 1-1
J
Joint Test Action Group (JTAG) interface 1-28 JTAG iii JTAG reset timing diagram 2-73 JTAG timing 2-71 JTAG/OnCE Interface signals Debug Event signal (DE signal) 1-30
G
General Purpose Input/Output v GPIO v, 1-2 Timers 1-2 GPIO timing 2-70 Ground 1-4 PLL 1-4 ground 1-1
M
maximum ratings 2-1, 2-2 Memory external interface 2-18 memory expansion port iii mode control 1-11 Mode select timing 2-10 multiplexed bus 1-2 multiplexed bus timings read 2-59 write 2-60
H
helpline electronic mail (email) address ii HI08 v, 1-1, 1-2, 1-14, 1-15, 1-17, 1-18, 1-19 Host Port Control Register (HPCR) 1-14, 1-
15, 1-16, 1-17, 1-18, 1-19
HI08 timing 2-54 Host Inteface 1-1 Host Interface v, 1-2,
1-14, 1-15, 1-17, 1-18, 1-
N
non-multiplexed bus 1-2
19
Not Recommended for New Design
I-2 DSP56307 Technical Data MOTOROLA
O
non-multiplexed bus timings read 2-57 write 2-58
R
recovery from Stop state using IRQA 2-16, RESET 1-11 reset bus signals 1-6, 1-7 clock signals 1-5 essi signals 1-20, 1-23 host interface signals 1-14 interrupt signals 1-11 JTAG signals 1-29 mode control 1-11 OnCE signals 1-29 phase lock loop signals 1-5 sci signals 1-26 timers 1-27 Reset timing 2-10, 2-14 reset timing synchronous 2-14 ROM, bootstrap iii
2-17
O
off-chip memory iii OnCE Debug request 2-73 module timing 2-73 OnCE module iii interface 1-28 OnCE/JTAG 1-2 OnCE/JTAG port 1-1 on-chip DRAM controller iv On-Chip Emulation module iii on-chip memory iii operating mode select timing 2-16 ordering information 5-1
P
package PBGA description 3-2, 3-3, 3-4, 3-7, 3-11 PBGA ball grid drawing (bottom) 3-3 ball grid drawing (top) 3-2 ball list by name 3-7 ball list by number 3-4 mechanical drawing 3-11 PCU iii Phase Lock Loop iii, 2-9 PLL iii, 1-1, 1-5, 2-9 Characteristics 2-9 performance issues 4-5 PLL design considerations 4-5, 4-6 PLL performance issues 4-6 Port A 1-1, 1-6, 2-18 Port B 1-1, 1-2, 1-16 Port C 1-1, 1-2, 1-20 Port D 1-1, 1-2, 1-23 Port E 1-1 Power 1-2 power 1-1, 1-3 power consumption benchmark test 3 power consumption design considerations 4-4 power management v Program Control Unit iii program memory expansion iv program RAM iii
S
SCI v, 1-2, 1-25 Asynchronous mode timing 2-62 Synchronous mode timing 2-62 timing 2-61 Serial Communication Interface 1-25 Serial Communications Interface v Serial Communications Interface (SCI) 1-1 signal groupings 1-1 signals 1-1 functional grouping 1-2 Single Data Strobe 1-2 SRAM read access 2-20 read and write accesses 2-18 support iv write access 2-20 Stop mode v Stop state recovery from 2-16, 2-17 Stop timing 2-10 supply voltage 2-2 Switch mode iii synchronous bus timings 1 WS (BCR controlled) 2-48 synchronous interrupt from Wait state timing
2-
16
synchronous reset timing 2-14
Not Recommended for New Design
MOTOROLA DSP56307 Technical Data I-3
T
T
table of contents ii TAP iii target applications v technical assistance ii Test Access Port iii Test Access Port timing diagram 2-72 Test Clock (TCLK) input timing diagram 2-71 thermal characteristics 2-2 thermal design considerations 4-1 Timer event input restrictions 2-68 interrupt generation 2-68 timing 2-68 Timers 1-1, 1-2, 1-27 timing Asynchronous Bus Arbitration mode 2-50 BSR 2-72 bus acquisition 2-51 bus arbitration 2-50 bus release 2-52, 2-53 DMA external source 2-17 DRAM access 2-22, 2-24, 2-26, 2-28, 2-30,
W
Wait mode v World Wide Web vi
X
X-data RAM iii
Y
Y-data RAM iii
2-31, 2-32, 2-35, 2-38, 2-41, 2-44, 245, 2-46 ESSI 2-63, 2-66, 2-67 GPIO 2-70 Host Interface 2-54 interrupt 2-10, 2-15, 2-16 JTAG 2-71 JTAG reset 2-73 mode select 2-10 multiplexed bus 2-59, 2-60 non-multiplexed bus 2-57, 2-58 OnCE module 2-73 operating mode select 2-16 Reset 2-10 SCI 2-61 SCI Asynchronous mode 2-62 SCI Synchronous mode 2-62 SRAM read and write 2-18 Stop 2-10 Stop state recovery 2-16 synchronous external bus 2-47 synchronous reset 2-14 TAP 2-72 TCLK 2-71 Timer 2-68
Not Recommended for New Design
I-4 DSP56307 Technical Data MOTOROLA
Order Number: DSP56307/D Revision 0, 8/10/98
Not Recommended for New Design
Mfax and OnCE are trademarks of Motorola, Inc.
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Not Recommended for New Design

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Price & Availability of DSP56307

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